contributed by St.J. Dixon-Warren, MEMS Sector Analyst

The iPhone 4 is the first portable consumer device to feature full nine degree-of-freedom (9-DoF) inertial sensing. Apple have done this by integrating a three-axis accelerometer and a three-axis gyroscope from STMicroelectronics (ST), together with an electronic compass from AKM.  The iPhone product line has moved steadily towards this goal with each successive model. Steve Nasiri and his Invensense colleagues discussed the benefits of 9-DoF sensing in some detail in a recent Whitepaper.

The original 2G iPhone, released in 2007, featured an ST 3 mm x 5 mm LIS302DL three-axis accelerometer. This provided the screen orientation function, by using the acceleration of gravity to determine the orientation, and it was also available to “app” developers for simple games. The iPhone 3G also only contained an accelerometer, but in this case Apple used the 3 mm x 3mm LIS331DL MEMS device, also from ST. Next up, the iPhone 3GS added digital compass capability by adding an AKM AK8973 electronic compass.  This provided improved GPS location functionality, even though (as described on an AKM web site) it required regular recalibration by waving the phone in a figure-eight motion  – no, it’s not a tai-chi app!

The iPhone 4 features an ST LIS331DLH three-axis accelerometer and an AKM AK8975 three-axis electronic compass. To get the 9-DoF, Apple added an ST L3G4200D three-axis gyroscope sensor, packaged in a 4 mm x 4 mm LGA package. 

Chipworks has examined all of the inertial sensors found in the iPhone product family and detailed reverse engineering analysis reports are now available. The following is a summary of our findings for the sensors found in the iPhone 4.

MEMS Sensors

According to ST the LIS331DLH is an ultra-low power, digital three-axis accelerometer. The package contains two stacked die, a V583A ASIC with 2007 die marks and a MEMS die with C5L12B 2008 die marks. Figure 1 shows the MEMS die, with its hermetic cap removed, illustrating the integrated XY sensor structure and a Z-axis sensor structure.

The XY sensor uses interdigitated finger capacitors to sense the motion of a proof mass that is constrained to move in the XY plane, while the Z sensor uses an underlying capacitor plate to sense vertical deflection of a proof mass mounted on a torsion spring. ST fabricated the part using their well-established THELMA process (Thick Epi-Poly Layer for Micro-actuators and Accelerometers). The THELMA process uses a thick top polysilicon layer (poly 2) to form the micro-machined electro-mechanical structures plus a thin buried polysilicon layer (poly 1) for connection to the bond pads, as well as for the bottom capacitor plate of the Z-sensor.

Figure 1 - ST Microelectronics LIS331DLH MEMS Die (click to enlarge)

The L3G4200D is also fabricated using essentially the same manufacturing process as is used for the LIS331DLH. The L3G4200D package contains a V654A ASIC, with 2009 die markings, stacked above a capped, integrated MEMS gyroscope die, which has GK10A 2009 die markings.  The L3G4200D is essentially a tuning fork vibrational gyroscope, where vibrational energy imparted to one degree-of-freedom of the mechanical structure is transferred to an orthogonal degree-of-freedom by rotation around an axis perpendicular to both the drive and sense modes of the device. Integrating three rotation sense axis into a single device represents a significant engineering achievement by ST.

Figure 2 is a photograph of the L3G4200D die. Banks of interdigitated drive capacitors, located on the left and right hand sides of the die, induce vibration of the tuning fork proof mass structures (see Figure 3). Rotation around the X and Y axis in the plane of the die (pitch and roll) cause an out-of-plane deflection of the proof mass. The poly 1 capacitor plates (beneath the proof mass, in Fig. 4) sense the deflections. Rotation around the Z axis (yaw) gives in an in-plane deflection, sensed by interdigitated capacitor plates located along the top and bottom edge of the die.

Figure 2 - L3G4200D MEMS Die (click to enlarge)

Figure 3 - L3G4200D MEMS Structures (click to enlarge)

Figure 4 - L3G4200D Buried Poly 1 MEMS Die (click to enlarge)

AKM Compass

The AK8975 found in the iPhone 4 is similar to the AK8973 found in the iPhone 3GS, although the 3GS part used a QFN package while the iPhone 4 compass used a wafer-level chip-scale-package (WL-CSP).

The AKM electronic compasses use integrated CMOS Hall sensor technology.  Figure 5 shows the AK8975 die photograph; the Hall sensor structure is near the bottom left corner of the die. It comprises four discrete Hall sensor devices, one for each quadrant of the approximately circular structure. A metal solenoid coil lies within the open area between the Hall sensor devices. Detailed inspection confirmed that the Hall sensor devices on the AK8975 are identical to those used on the AK8973.

Figure 5 - AK8975 Die (click to enlarge)

Hall devices are sensitive only to the component of the magnetic field vector perpendicular to the surface of the die. The AKM electronic compass products thus incorporate a magnetic concentrator that serves to bend magnetic field lines parallel to the die surface, to obtain a component perpendicular to the surface. Figure 6 presents a plan-view X-ray of the 2 mm x 2mm AK8975, indicating the location of the magnetic concentrator.

Figure 6 - AK8975 WL-CSP Package X-Ray (click to enlarge)

Cross-sectional analysis of the packaged AK8975 shows that the magnetic concentrator, formed using a FeNi alloy, is mounted beneath the die (Fig. 7). The location of the Hall Sensor device and the solenoid coil are indicated on the micrograph.

Figure 7 - AK8975 Magnetic Concentrator Cross-Section (click to enlarge)

The integration of 9-DoF sensing into the iPhone 4 will, with certainty, enable new applications. The inclusion of the gyroscope raises the accuracy of motion sensing, for example for gesture recognition, while the incorporation of the compass improves navigation functionality. 

The iPhone 4 has many other sensors, which incidentally is perhaps why it is so popular. The specifications on the Apple web site disclose the digital compass, gyroscope and accelerometer, discussed above, plus an LED-based proximity sensor and an LCD-based ambient light sensor that control the power to the screen, and multiple microphone sensors. Chipworks found three MEMS microphones, a Knowles and an Infineon inside the iPhone 4, plus another Knowles microphone in the ear bud wires.  

The dominant sensor on the iPhone is, of course, the touch screen. This sophisticated sensor uses an Apple-branded 343S0499 Texas Instruments touch screen controller.

Finally, the iPhone 4 includes two OmniVision CMOS image sensor cameras, and OV5650 backside-illuminated (BSI) image sensor for the primary camera and a VGA secondary camera, likely the OV7738.

A question of interest is what new sensors will Apple include next? Possibilities might include a pressure sensor for barometric pressure and altitude measurements, although in this case the benefits to the user might be marginal.

It may be the case that Apple has exhausted the ranged of sensors that would provide significant benefit to the users. The iPhone 4 provides functionality that corresponds to three of the five the human senses including vision, hearing and touch. Is it likely that we would want our iPhone to be able to taste and smell?

Recent Chipworks reports referencing technology found in the iPhone

A month ago we blogged about the apparent similarity between TI’s Sitara AM3715, and their OMAP3630.  Now we’ve got hold of the OMAP chip and looked at it, and lo and behold, they do look like the same, or very, very similar, chip.

As we noted earlier the mask marks on the two die are almost the same:

AM3715                                                OMAP3630

As you can see, the AM3715 has mask mark F781773, and the OMAP is F781773A, although with different dates, 2009 and 2010 respectively.  Now we do have a delayered OMAP, so that we can compare the block layout, and they look pretty much the same to me:

AM3715 M1                                                     OMAP3630 Poly

We recently got hold of TI’s Sitara AM3715, a 45 nm application processor with a 1 GHz ARM Cortex A8 core and a POWERVR SGX™ graphics accelerator, among other capabilities, but of course, so does the OMAP3630 (not coincidentally similar to Apple’s A4 chip from the Ipad and iPhone 4).

The Sitara range of processors is compatible with the OMAP3 architecture, but unlike OMAP's, doesn’t appear to be targeted at the mobile phone segment. The AM3703 and AM3715 (both are from the AM37x family) are “suitable for a wide variety of applications, such as portable data terminals, portable medical equipment, home and building automation, navigation systems, smart displays, human machine interaction (HMI) industrial interfaces, and other applications which demand require high performance, low power processing capabilities. The AM3715 offers a nearly 40 percent increase in ARM performance, double the 3D graphics performance, and lower power by up to 30% when compared to previous generations.”

Both have other parallel features, though described differently enough (and vaguely enough) to make it difficult to do a side-by-side feature comparison based on documentation. The thing that really triggered our supposition was the similarity of the mask marks on the two dies:

As you can see, the AM3715 has mask markings of F781773, and the OMAP has F781773A, although with different dates, 2009 and 2010 respectively. We don’t have a full die image of the OMAP3630, but we do have the 65 nm OMAP3530, and the layouts are definitely similar.

We would expect some layout differences, since the analog and digital parts of the chip scale differently, but the overall chip size has scaled – the AM3715 is half the size of the OMAP3530.

A different bonding pattern could account for functional differences in the packaged device. And using the same chip design for similar functionality in multiple market segments would certainly help keep costs down.

When we get the OMAP3630 we’ll know for sure!

Past public teardowns on Apple mobile devices from Chipworks and others, have tended to focus on the lack of state-of-the-art silicon. They pointed to Apple's success as a result of good systems integration and a holistic experience. While this presented headline-worthy analysis, it downplayed the importance of the truly amazing semiconductor innovation. Chipworks goes inside what makes the iPhone 4 so amazingly cool - and it isn't just the great new role playing app you just installed off the app store.

The acute iPhone 4 shortages caused us no end of pain as we had buyers lined-up in Japan, New York, and California only to get it two days before the proposed launch date here in North America. This initial look is a basic teardown (in partnership with iFixit), without die-level analysis of all the key chips. But more is to come, so register now to be updated. 

Discover more on the iPhone 4 teardown page. 

Apple A4 microprocessor

Metal gates are back. First Intel used them in its microprocessors and now Winbond in its latest DRAM.

To the broader market, the move to metal gates is understood as being based on pure electrical performance (i.e., speed), but in the case of the DRAM device, this new technology also suggests a significantly lower manufacturing cost. By way of a history lesson, metal gates haven’t been used in production for several decades because the lack of self-aligned source/drains added unnecessary process complexity. Ironically, in this product, they actually simplify the process.

This DRAM technology is called “Buried Wordline” (bWL) and is licensed from the now defunct Qimonda. The Winbond 1 Gb SDRAM features a 0.025 µm² cell in a 6F² layout. Sinking the wordline below the substrate surface eliminates stray capacitance between the wordline and contacts, and reduces the bitline/wordline capacitance, ultimately lowering power consumption.

All of the other major DRAM manufacturers, including Elpida, Hynix, Micron, and Samsung, have maintained generally the same overall process design from DDR to DDR 3 SDRAMs, as the devices were scaled from 90 nm to 40 nm to achieve higher capacity SDRAM memory. All of these major DRAM manufacturers use some flavor of recessed channel array transistor (RCAT) wordline transistors, with a relatively complex sidewall spacer structure, a separate metal level for bitline, and multi-level poly plugs to contact capacitor cells to wordline transistor source/drain (S/D), which are in many instances offset from each other and from the capacitor cells. Further, most of the SDRAMs use double-sided capacitor tubes for their DDR 3 SDRAMs, supported by an extra dielectric layer near the top plate for mechanical stability.

Winbond’s SDRAM process design, at least at the 65 nm node, is significantly simpler. By burying the metal gate wordline, there is no need for a complex sidewall structure and separate metal level for the bitline. The silicided poly layer that is used for transistor gates in the peripheral circuitry is also used for bitlines in the memory array. This reduces the number of poly plug levels used to contact the capacitor cells to the wordline transistor S/D to just a single level, and reduces the associated complexity of plug alignment and plug-to-plug resistance due to carefully designed plug-to-plug offsets. The process complexity is further reduced by using dummy wordlines instead of STI to isolate active wordlines (which may make it harder to scale down to 40 nm and below due to increased cross talk).

The simplified process can be observed in both cross section and planar view of the capacitor. Interestingly, in the lower part of the stack, ZAZ (zirconia/alumina/zirconia) high-k dielectric is only used on the inside of the TiN cylinder, while the upper section uses ZAZ on both the inner and outer surfaces. This structure gives a lower overall cell capacitance compared with the full double-sided structure, but presumably it is still sufficient to give a sense-able signal to the bitline. However, the simplified process should give an excellent cost and yield advantage; this design may well make a very competitive part for Winbond for all but the most densely populated boards. And with devices like the iPad seemingly having tons of extra room for electronics – cost may well be the deciding factor for a lot of electronics.

Capacitor stack in the Winbond 65 nm 1 Gb SDRAM

Plan view sections of the Winbond 65 nm 1 Gb SDRAM capacitors, showing the upper (bottom image) and lower sections

by Ray Fontaine, Image Sensor Analyst

I mentioned in a previous blog that image sensor companies would be deploying  BSI technology when their targeted applications demanded it.  Admittedly, I was mostly thinking about mobile phone applications where form factor and ever shrinking pixel pitch seems to be the primary driver for BSI.

As noted in several news articles, nicely consolidated in Image Sensors World blog postings, BSI is also making headway in digital still camera (DSC) and video camera applications.  The latest Sony BSI design win that we’ve seen is from Casio’s EX-FH100 EXILIM DSC.  In fact we documented a number of interesting and innovative devices in a product teardown on this camera.

This product is positioned as a high speed EXILIM camera with a wide-angle 24 mm, 10x optical zoom lens.  It offers a maximum burst rate of 40 fps for still images (maximum image size of 9.0 Mp, maximum capacity of 30 frames), and also a 1,000 fps high-speed movie mode for slow motion movie functionality.  

The image signal processor (ISP) is a Sony CXD4122GG 2^nd generation camera system chip designed for use with Sony Exmor R CMOS image sensors (CIS).  The CXD4122 is capable of high-speed imaging of up to 10 Mp images at 50 fps, and high-speed video at 240 – 1,000 fps.

Sony CX412D2GG Image Sensor processor

Before getting into the CIS silicon, it is worth noting that Sony’s IMX050 BSI sensor displays quite a lot of innovation at the packaging level.  We’ve previously seen the Sony BSI die elsewhere, but this is the first time we’ve seen it packaged with embedded passive components in the chip carrier.  Sony claims the new miniaturized package is 30% smaller than their existing solution.  A detailed process report is underway to study the packaging.

Planar and Side X-Ray of Sony IMX050 CIS – Embedded Passives

The IMX050 is a 1/2.3” optical format, 1.65 µm pixel pitch CIS featuring Sony’s 2^nd generation BSI process technology and column-parallel A/D conversion design.  Sony’s Exmor-R backgrounder describes the inadequacies of CCD’s for this application as being the driver for their high-speed CIS development.  The implementation of BSI also resulted in an approximate 2x increase in sensitivity as compared to an equivalent front-illuminated pixel.  

Sony presented their high-speed BSI technology in February at the 2010 International Solid-State Circuits Conference (ISSCC).  Our preliminary findings indicate the CIS from the ISSCC presentation is a match to the Casio sensor.  Essentially, the new Sony technology hits across three industry/consumer sweet spots: high-speed readout, high resolution, and high signal-to-noise (SNR).  A full imager process review (IPR) report will provide coverage of the high-speed BSI pixels and 0.14 µm copper fabrication process.

Sony IMX050 CIS – 2010 ISSCC Paper 22.9 (l), Chipworks Back-of-Die Photo

In summary, Sony have a very definite strategy to service high-performance, high value consumer CIS applications.  As low resolution, small pixel mobile sensors have become a commodity, Sony has chosen to play at the other end of the spectrum where technical innovation is likely to derive higher margins.  As seen in this teardown example, they are also able to grow their business by winning designs for their technology in their consumer electronics competitors.  One final observation is the continued displacement of CCD’s in high-end DSC’s, as we’ve already seen in some Canon and Sony point and shoot cameras. 

_________________________

Click here for a list of reports related to the Casio Exilim.

Touch Screens Everywhere

Computing is getting closer to the consoles we see on old episodes of Star Trek TNG, with everything seeming to go touch screen these days. It is actually uncanny how the touch screens resemble the shiny black sleek things that Captain Picard used to use. The latest hot gadget to leverage this technology is, of course, the Apple iPad. 

Example of a Star Trek touch screen: (http://www.startrek4u.com/special/multimedia/lcars/curry/enterprise-e-engineering-ne.png)

Enabling technology is an important precursor to great systems and consumer acceptance of new and nifty products. For example, from a semiconductor standpoint, you could argue that the driving force behind the success of devices like portable music players was the availability of huge amounts of small and inexpensive memory. 

Now with touch screens, the enabling technology is powering a whole new type of application development for systems and software design. The combination of smart phone ubiquity and emerging tablet computing opens billions of new sockets, where the secret sauce for the next killer app is once again the semiconductor technology that is beneath.

With a market forecasted to grow to $9 billion dollars by 2015 (from $3.6 billion in 2008), there has been a flurry of activity in this sector, with some analysts reporting over 170 suppliers in the supply chain today (source = DisplaySearch).

To illustrate the innovation we will use Apple – a current (and deserved) media darling who has done an exemplary job integrating touch screen technology.  

What makes a touch screen controller work?

The most popular technology used in touch screens is the resistive 4-wire and 5-wire approach, due to low cost and simple interface electronics. There is also a recent notable increase in overall shipping of products based on the Projected Capacitive Touch (PCT) approach. This latter technology is used by Apple and others, including the Samsung Pixon12 and Sony Ericsson Satio.

Controlling the screen is managed through a variety of chipset solutions. Staying with our example, Apple used to use a 5-chip solution in the original 2G phone, evolved to a 3-chip solution, and now its latest devices use a single Texas Instruments chip – the 343S0487. This latest TI chip has documented design wins in the iPod Touch, iPhone, and Magic Mouse – but notably not the iPad.

Getting the required touch functionality onto the 343S0487 single chip was facilitated by fabricating at 90 nm. This gave the required density to put all this functionality into a small footprint and at a low cost. This device has a contacted gate pitch of ~341 nm and a metal 1 half pitch at ~155 nm. The device further features five metals and an aluminum RDL. By comparing the CMP, we do see a fill pattern characteristic of Texas Instruments, and can conclude that the device is likely manufactured within one of its fabs.

In fact, TI has also been gaining some other big socket wins in this industry, notably the Motorola DROID resistive touch screen (using TI’s TSC2046 4-wire touch screen controller with low voltage digital I/O). What is different about this chip versus the one found in the Droid is that the device made for Apple contains over 50% digital components and memory versus a simple analog chip that looks very similar to the Burr Brown version made 10 years ago (TI acquired Burr Brown). Getting all of Apple’s advanced features clearly requires some relatively heavy processing power.

To see an annotated die photo of the TI 343S0487, you’ll need to visit our page promoting die photos of several of the touch screen controllers we have in inventory (scroll to bottom of page).

Although the focus of this article has been on Texas Instruments, a number of other innovative suppliers are in this market, including Cypress, Analog Devices, Broadcom, Synaptics, eGalax_eMPIA , and others. In the end there will, of course, be winners and losers.  However, as the market matures, there is plenty of opportunity for all of these players to succeed with their own unique spin on the technology.

Evaluating the Software in Automotive ECUs

contributed by Stanko Vuleta

Reverse Engineering Software and Systems

As part of our patent support business, Chipworks applies software reverse engineering to generate evidence of patent infringement, which is used by IP groups and outside counsel in patent licensing negotiations and litigations. This evidence is in the form of a claim chart which maps relevant patent claim elements to the infringing product. We apply software reverse engineering to analyze and document infringement on a wide variety of products, from consumer electronics to communication devices and automotive systems.

We recently went inside an automotive electronic control unit (ECU). These ECUs comprise a wide range of units like the powertrain control module (PCM), body control module (BCM), electric power steering (EPS), airbag control unit (ACU), or electronic brake control module (EBCM). In light of the recent media attention targeting the automotive industry, we thought it would be interesting to share some of our findings in relation to the perceived quality of the systems software against other semiconductor-based systems we have analyzed.

Since our overall findings are a bit mixed, we will spare the blushes of the leading automotive companies by not publishing the make or type of module we analyzed.

Reverse Engineering an Automotive Module

First we disassembled the module, reverse engineered the PCB, scoped its signals while operational, and reverse engineered its software.  

Two types of software analysis were done. We extracted the raw binary code from the module and analyzed it statically (called “dead” code analysis). We also analyzed the code while it was in action on the target device (called “dynamic” or “live” code analysis).

We then rated several aspects of the unit (e.g., physical protection, code complexity) for quality. The results were surprising to us.

Physical Protection: Good

The module has a heat sink which also plays the role of a mechanical cover. The CPU detects the presence of the module and stops running the code if it is removed. Below is an example of one of the holes used for screwing the module to the PCB.  

Note the resistor connecting the screw pad to the CPU.

Code and Data Space Protection: Good

The code space is checked for corruption and tampering by calculating and checking a CRC over the complete code space. The twist on this particular implementation is that there are several routines doing similar CRC checks, making tampering with the code more difficult.

The content of the RAM data space cannot, of course, be checked for correctness since it changes all the time. Instead, the memory integrity is checked by writing and reading back standard 0xAA – 0x55 patterns in the background. The obligatory enforcement of the atomic instructions has been observed here.

Compared with other consumer and communication devices that come across our desks, both the code and data space protection were a notch higher.

Code Complexity: Bad

Inner workings of the code have been analyzed, and a number of software routines completely dissected. The surprise here was just how much code was created for what was supposed to be simple processing of a few sensor values. A lot of the code improved sensor resolution and produced more precise reading; correction, normalization, and adjustment routines were abundant.

This left us with a question – why was it necessary to go to great pains to provide 0.003% precision when 0.3% would have sufficed for the purpose?

This observation was further confirmed by the sheer number of routines in the code – over 700 in total. Around 200 of them were involved in the comparatively simple task of processing two sensor inputs and outputting two variables. This certainly looks like overkill.

The calling tree, showing which routines call which others, looks rather intimidating.

The overwhelming impression was that precision was put far ahead of code simplicity.  Occam’s razor was rather dull in the process of this code development.

Debugability: Bad

A good coding practice is to sprinkle the code with debug logs. Granted, they do increase the code size, but they can also save your bacon when you need to debug a problem in the field on a live system. Usually, the execution of the debug logs is skipped and turned on only when needed.  

We did not see evidence of debug logs in this code. 

The CPU in question did not have a JTAG or any other debug port. The only way to debug it effectively is to use an in-circuit emulator (ICE). The only problem with the ICE is that the CPU needs to be completely removed and replaced with a bulky ICE module. Such a contraption can not fit mechanically in the narrow space provided for the module. Couple this with the above mentioned physical protection, and the result is a very difficult setup to debug in the field.

Error Handling: Ugly

Another good coding practice for mission critical applications is to check for software errors and log any found. A balance needs to be achieved between too much error checking and too little. Too much leads to code bloat (more code, more bugs), and too little will let code bugs lurk undetected.

The voluminous code we inspected is certainly not a result of too many error checks. In many of the routines inspected, there were no checks for software errors. 

We did, however, find checks verifying the raw sensor values and final output values, but not much more. Even these errors were not logged immediately when they were detected, potentially making the debugging more difficult. 

However, the most worrisome error checks were those where values were checked if they were outside a maximum range allowed. One would think that alarm bells would be going off upon detecting any such errors, and they would be logged and appropriately handled. Instead, all that was done was to simply cap the value to the maximum (or minimum) and forward it on as if nothing had happened!  

Contributed by Jefferson Chua

Chipworks recently extracted and analyzed the circuits from Alpha and Omega’s AOZ9007 battery protection IC. This chip is used for lithium-ion rechargeable battery packs, and competes with products from Sony, Texas Instruments, Fairchild Semiconductor, ON Semiconductor, Analog Devices, and Maxim Semiconductor.

When it first landed on my desk, I figured that it was “just another IC with comparator circuits” – ho hum.

However, once the analysis progressed I found some surprising things. 

The AOZ9007 battery protection IC consists of a two-stacked die. The battery protection package includes a power control integrated circuit stacked on top of an integrated dual common drain MOSFET. With this configuration, not only will the battery protection IC have better performance, it will also be smaller. Effectively reducing the area of this device, making it suitable for power controllers where size is an issue.

Figure 1: Alpha and Omega AOZ9007 battery protection IC x-ray and die photos

Also, this is not just “another IC with comparator circuits.” These comparators act as detectors that prevent the single cell lithium-ion rechargeable battery packs from overcharge, over discharge, and over-current conditions. Hence, they are sensors that will put more life into your battery.

Figure 2: Detector circuits (circled) for the battery protection IC

The power control IC consists of a number of constant-current logic gates such as inverters. This is in contrast to “normal” inverters with the PMOS and NMOS source connected directly to VDD and GND. These constant-current inverters are used not only in the oscillator but everywhere that constant-current is required.

Figure 3: Logic circuit showing the constant-current gates

We extracted the full device, including the oscillator, counter, logic circuits 1 and 2, short-circuit detector, etc. Clients in this market will find the Alpha and Omega AOZ9007 battery protection IC to be a very compelling industry benchmark.

TI Touch Screen Controller Replaces Five Chips from Original iPhone Design

 A glimpse into the world of touch screen controllers

by Jerico N. C. Garcia

What does the Apple iPhone 3GS have in common with your regular ticketing kiosk? How about the Nintendo DS handheld game console and a regular bank teller machine? All of these products use touch screen technology solutions in one form or another, as provided by the leading controller suppliers for the last several years.

It has been generally accepted that the term refers to the ability to interact physically with what is shown on a display, via touch or contact, using either a finger, hand, or pen. The popularity of this application is mainly due to its ease of use, as well as the intuitive interfaces enabled by its use. With a market forecasted to grow to $9 billion dollars by 2015 (from $3.6 billion in 2008), there has been a flurry of activity in this sector, with some analysts reporting over 170 suppliers in the supply chain today.

The most popular technology used in touch screens is the resistive 4-wire and 5-wire approach, due to low cost and simple interface electronics. There is also a recent notable increase in overall shipping of products based on the Projected Capacitive Touch or PCT approach. This technology is used by Apple, for its iPhone and iPod Touch, and others including the Samsung Pixon12 and Sony Ericsson Satio.

Looking closer at the perennial (can I say that?) media favorite, the Apple iPhone, touch screen development has undergone a radical change from the 2G all the way to the 3GS model. Back in the 2G era, the touch screen controller function was implemented using a number of ICs mounted on a single mini PCB. The ICs include Apple’s custom sensing IC (fabricated by Broadcom with die markings BCM5973A), a Texas Instruments (TI) driving IC (CD3238), an NXP MCU (LPC2221 – 32 bit ARM Core), a Hosonic crystal, and an ATMEL EEPROM. 

Figure 1  Front and Back of Touch Screen Board from the iPhone 2G

The second generation 3G did not have the miniPCB. Instead, the Sensing IC, MCU, EEPROM, and crystal were all incorporated into Broadcom’s BCM5974 touch screen controller IC, while TI’s CD3239 replaced the CD3238.

The latest iPhone 3GS model appears to have integrated all five of the 2G’s touch screen controller functions under a single custom IC, with package markings 343S0464. The die markings F761586C indicate that winning this high volume socket, and also the related iPod Touch and Magic Mouse sockets, is a coup for Texas Instruments. Getting the required functionality onto a single chip was facilitated by fabricating at 90 nm. In fact, TI has been gaining some other big socket wins in this industry, notably the Motorola DROID resistive touch screen (using TI’s TSC2046 4-wire touch screen controller with low voltage digital I/O).

Figure 2  iPhone 3GS Board Showing Single Chip for Touch Screen Control

Figure 3  Die Photograph of TI Touch Screen Controller Delayered to Bottom Metal Layer

What is most impressive is that each of these wins shows TI’s breadth of technology to serve this market. In the case of the iPhone, TI has delivered a chip that is over 50% digital and memory. In the Droid, TI won with a tried and true design that is almost entirely analog circuitry, and appears to be the same as the touch screen technology from TI's acquisition Burr-Brown that Chipworks analyzed 10 years ago; though we haven’t extracted any circuitry on today’s chip, you can see the layout is very similar.

Figure 4  Comparison of Burr-Brown ADS7846 and TI TSC2046 Touch Screen Controllers

Of course, now we have Apple's latest product launch, the question will be who wins the controller socket in the iPad?  This is a hot and heavy sector these days, and with new entrants like Synaptics getting the design win in the Google Nexus One, nothing can be taken for granted.

In all the hype since yesterday about the iPad, and the screen shots from the Apple video showing the app's processor, leading to speculation about whether it is designed by PASemi or not, or whether it has an ARM A7, A8, or A9 core; or whether it was fabbed by Samsung or not, nobody has commented on the other chip that was in view.  I've shown it below in our screen shot from the Apple video - if you squint, you can see the NXP logo upside-down on the outlined part:

So it appears that the one solid piece of information we have so far about the innards of the iPad is that NXP have got a socket win, likely for a power management part.  NXP had chips in the first iPhone, and in later products, so this continues their presence in the Apple BOM listing.

The other bit of information that you can infer from the image is that the processor package doesn't look like the package-on-package stack used for the processors + DRAM in iPhones and iPod Touch players up until now.  I guess in the iPad there's enough real estate for separate DRAM chips, so that bit of extra expense isn't needed.

Now we wait for a real one to tear down!

This has also been posted on our Chipworks Inside Angle blogsite.

In a few days time the great and the good of the electron device world will be gathering in Baltimore for the 2009 IEEE International Electron Devices Meeting.  To quote the conference lead release, “IEDM is the world’s premier forum for the presentation of applied research in microelectronic, nanoelectronic and bioelectronic devices.” 

From my perspective, focused on chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

In the last few days I’ve gone through the advance program, and here’s my pick of what I want to try and get to, in more or less chronological order.  As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Monday morning we have the plenary session, and we get to the delegates’ papers after lunch.  Session 5 on memory technology is dominated by Numonyx, with three out of seven papers (5.1, 5.3, and 5.7), on their phase-change memory (PCM) technology. Since we looked at their 90-nm 128 Mb PCM part earlier this year, I’ll be sure to take those in, especially the last paper of the session which discusses their 45-nm 1-Gb part.

Tuesday morning there’s another bunch of memory papers; IBM continues (11.1) the scaling of their embedded trench DRAM to the 32-nm node; and in paper 11.6 Qualcomm and TSMC are looking at 45-nm MRAM. 

There is also a session on 3D technology, with TSMC (14.1) discussing through-silicon vias (TSVs), and a paper by Fujitsu et al (14.6) on ultra-thinning wafers down to 7 µm.  Back at Semicon West, Jerry Bautista of Intel put up this slide of their Terascale project packaging:

It probably doesn’t show too well in a web image, but the wafer in the cross-section at the bottom right is about eight microns thick.  And given Samsung’s recent announcement of 15-µm thick dice in eight-stack flash-memories, we’re in for some super-thin chips in the not too distant future.

In the afternoon there’s a special session of invited papers on the design issues created by advanced CMOS processing (also known as design-for-manufacturability, or DFM), something that we’ve noticed and commented on in the recent generations of chips.  In fact, this topic is hot enough that we’ve drafted a DFM report on the Intel 32-nm. Session speakers are from IBM, Intel, TSMC, and NEC, and others.

In parallel sessions we have a SWOT (strengths, weaknesses, opportunities, threats) analysis from IMEC of germanium as a channel material (19.3), and a Sony paper (22.8) on a 0.9-µm pitch image sensor, designing using a “constant-light-diffraction-scaling methodology”.

Come Wednesday, the last day of the conference doesn’t slow down.  The morning is filled with advanced CMOS papers, two from Intel (28.1 and 28.4), and others from the IBM consortium (28.2) and UMC (28.3).  I have to say I’m looking forward to the second Intel paper, to see if there’s any clarification on the NMOS stress mechanisms in their 2^nd generation HKMG process. 

After my blog back in October, I’ve come to the conclusion that we don’t have e-SiC; talking to other folks in the business, it seems that it’s still too difficult to get the carbon to stay in place in the silicon lattice; and we can’t see any carbon that is definitively associated with the source/drains.  Hopefully we’ll find out next week!

In another morning session 27, on 3D memory, there’s a joint Intel/Numonyx PCM paper, and an invited review paper by Al Fazio, also from Intel.

Even though folks tend to take off home in the afternoon, I shall be there until the bitter end - session 34 is on flash memory, with reliability papers by Samsung (34.2), Toshiba (34.4), and Macronix (34.6).  Parallel session 36 covers off the interconnect stack, with three NEC presentations of note (36.1 - with Toshiba, 36.4, and 36.5).

So as always, no peace for the curious!  And I have to blow my own trumpet a bit, since I will be hosting the annual Chipworks ‘Lunch and Learn’ across the courtyard at the Marriott on Monday December 7^th at 12.00 noon.  We’ll be discussing some of the year’s chips, likely the ATI/TSMC 40-nm part, maybe a Freescale/IBM 45-nm chip, and of course we’ll have some of the details we found in Intel’s 32-nm Westmere part.  For anyone that want to come along, registration is here, or at the door.

Update: we’re not the only ones hosting at the Marriott - Applied Materials is holding a symposium on the future of NAND flash on Tuesday evening, and ASM is having a lunch seminar on ALD on Wednesday.  It will be a busy conference - hope to see you there!

Contributed by: St.J. Dixon-Warren

Analog Devices recently launched the digital ADXL346 3 mm x 3 mm x 0.95 mm thick, three-axis accelerometer. This device competes directly in the consumer electronics market with the Bosch SMB380, the STMicroelectronics LIS331DL, the Freescale MMA7660 and the Kionix KXSD9, which are also available in small footprint 3 mm x 3 mm packages.  Chipworks analysis suggests that the launch of this new device was made feasible by Analog Devices new MEMS foundry strategy.

Since the introduction of the ADXL50 in 1991, Analog has built their MEMS inertial sensors using their iMEMS technology, which cleverly integrated the micromechanical structures and ASIC circuitry on a single die. Both the 3 mm x 5 mm ADXL345, which was discussed recently in a posting on the MEMS Industry Group Blog, and 3 mm x 3 mm ADXL346 contain a separate MEMS and ASIC dies, and they thus represent a marked change in Analog Devices MEMS strategy.  This new strategy allows Analog to separate the MEMS chip design from the ASIC design. They can choose to have the ASIC fabricated at a foundry. Chipworks’ analysis has found that the ADXL346 contains the same MEMS die as the ADXL345. Analog Devices has used some clever engineering to fit the two dies into the smaller footprint ADXL346.

Figure 1 ADXL345 Package Top (3 mm x 5 mm)

Figure 2 ADXL346 Package Top (3 mm x 3 mm)

The corresponding plan-view x-ray photographs are shown in Figure 3 and Figure 4.  The footprint for the MEMS and ASIC dies inside the ADXL345 is 2.8 mm x 3.3 mm, which is too large to fit inside the 3 mm x 3 mm ADXL346 package.

Figure 3 ADXL345 Package X-Ray

Figure 4 ADXL346 Package X-Ray

Two strategies have been used to fit the MEMS and ASIC dies inside the ADXL346. First, Analog has designed a new, smaller ASIC die for the ADXL346. The ADXL345 uses the 1.37 mm x 2.17 mm XL345C ASIC, while the ADXL346 uses the 56% smaller 0.86 mm x 1.94 mm XL346 ASIC. As mentioned, both parts use the same 1.25 mm x 1.47 mm MEMS die.  These parameters are summarized in Table 1. 

Shrinking the ASIC appears to have been insufficient to fit the two dies into the 3 mm x 3 mm ADXL346 package, and hence Analog has also rotated the MEMS die 90° with respect to the ASIC inside the ADXL346 package and then wire bonded the MEMS die to the package substrate, rather than directly to the ASIC. The interconnection to the XL346 ASIC is through wiring in the package substrate. Only a ground wire to the MEMS die lid connects directly to the ASIC. Chipworks has not seen this strategy used previously.  The Bosch SMB380, the Freescale MMA7660 and the Kionix KXSD9 have the MEMS and ASIC mounted side-by-side with direct wire bond connections from the MEMS to the ASIC. The STMicroelectronics LIS331DL stacks the ASIC over the hermetic lid of the MEMS die (this strategy requires thinning the die to achieve a 1 mm thickness).

The rapid appearance of the smaller footprint ADXL346 a few months after the launch of the ADLX345, shows the benefit of Analog Devices new strategy. They were able to rapidly shrink the area of the ASIC, while keeping the MEMS die the same, thus achieving the smaller 3 mm x 3 mm package size required for the consumer electronics market.  It is worth noting that Analog was an early to the market, in 2006, with a three-axis accelerometer, the ADXL330, which was fabricated with their integrated iMEMS process and packaged in a 4 mm x 4 mm x 1.2 mm thick package. It would appear that the complexity of their integrated iMEMS process meant that they could not easily achieve a 3 mm x 3 mm x sub-1 mm thick package without changing their MEMS strategy.

Table 1 ADLX345 versus ADXL346 Comparison

Chipworks Reference Reports

• EXR-0910-802 Analog Devices ADXL346 3-Axis Accelerometer MEMS Exploratory Report
• MPR-0907-802 Analog Devices ADXL345 Digital Accelerometer MEMS Process Review
• MPR-0708-801 Bosch SMB380 Accelerometer MEMS Process Review Report
• EXR-0905-802 Freescale MMA7660FC 3-Axix Accelerometer MEMS Exploratory Report
• EXR-0902-811 Kionix KXSD9 3-axis Ultra low power digital accelerometer MEMS Exploratory Report
• MPR-0809-802 STMicroelectronics LIS331DL  Accelerometer MEMS Process Review
• PPR-0602-801 Analog Devices ADXL330 3-axis Accelerometer Process Review Report (MEMS)

Recently we at Chipworks managed to get our hands on some of Intel’s hot (not to say smoking!) new 32-nm Clarkdale/Westmere microprocessors.  Needless to say they went straight into the lab, so that we could get a look at the changes from the 45-nm high-k, metal gate (HKMG) generation.

To be honest, I was expecting more or less a straightforward shrink of the earlier process, possibly with a lower-k intermetal dielectric; however, while it’s a bit speculative, I don’t think we can say that.

However, let’s start with some numbers.  At IEDM [1] last year, Intel announced a contacted gate pitch and M1 – M3 (1x) metal pitch of 112.5 nm; – we see ~113 nm, so the same, allowing for measurement error.  SRAM cell size was given as 0.17 µm², exactly what we have found.  The physical gate length was reduced from 35 nm in the 45-nm process to 30 nm in the new generation; the smallest we have found so far is ~28nm. (more...)

For the complete article please visit the Chipworks Inside Angle blog hosted on Semiconductor International.

To learn about or order the Chipworks Reports on this technology please visit the Intel 32 nm Westmere landing page.

Fig - 32 nm on left, 45 nm on right

Last week I was at the Custom Integrated Circuits Conference in San Jose, giving a paper on "Design-for-Manufacturing Features in Nanometer Logic Processes – A Reverse Engineering Perspective".  A few days before the conference, I was contacted by a sharp-eyed journalist from IEEE Spectrum who was curious about the paper, and in due course an article "New Chips Loaded With Dummy Parts" appeared on the Spectrum website.  It's a very readable explanation of what's going on in the business these days, so I reproduce it below.  Many thanks to Anne-Marie for her patience while I went through all of this stuff!

New Chips Loaded With Dummy Parts

Reverse-engineering firm reveals how "design for manufacturability" is changing the look of ICs

contributed by Ray Fontaine, Image Sensor Sector Analyst

Canon and Nikon have long been the twin DSLR giants. A 2008 BCN Japan review showed each to have a 39% market share of the Japanese DSLR market (Charts 1 and 2). These numbers would naturally fluctuate for worldwide DSLR sales, but certainly Canon and Nikon are dominant.

Chart 1: 2008 Japanese DSLR Market Share (from BCN Japan/SlashGear) [1]

Chart 2: 2008 Japanese DSLR Market Share (from BCN Japan/SlashGear) [1]

A quick search of DSLR growth projections yields a range of analyst predictions. In January, the Camera and Imaging Products Association (CIPA) forecasted a 6.8% increase (for 2009) in DSLR sales despite world wide economic woes. The projection for interchangeable lens cameras is a year-over-year increase of 8.6% for 2010 and 7.0% for 2011 [2].

It is not hard for Canon or Nikon to predict encroachment on its market space by other camera makers. The segment that seems to offer the most growth potential is enthusiast/semi-pro grade class DSLRs with HD video functionality. The question should be asked, in what area are the challengers being innovative to give them competitive performance and feature sets? Is there much more that can be done with the image sensor silicon itself, or does attention have to be turned to the systems level for innovation? We’ve analyzed the image sensors from the recent Pentax K-7 and Panasonic DMC-GH1 and compared them to their respective predecessors. In both cases, we’ve found a tremendous amount of innovation in the image sensor fabrication processes, not to mention the sensor design. 

The Pentax K-7 replaces the K20D and features 720p HD movie functionality [3].  The first generation Samsung sensor from the K20D was itself full of firsts. The Samsung S5K1N1FX (K20D) was the first DSLR CIS we found to use copper metallization in the back end of line (BEOL). Figure 1a shows cavities that were etched into the pixel BEOL, and subsequently filled with an organic spin-on planarizing film. This was a trick borrowed from Samsung’s small pixel development; Chipworks first observed Samsung implementing this in their
1.75 µm generation pixels. The 5.0 µm pitched pixels used by the K20D and K-7 also feature an oxide cap over the organic microlenses. In addition, we also discovered pitch-matched metal-insulator-metal (MIM) capacitors in the column circuits. Figure 1b shows the MIM capacitors from the S5K1N1FA (K-7).

With respect to innovation since the K20D, the process analysis of the K-7 CIS indicates a change in packaging, major re-engineering of the wells and substrate, a modified pixel poly and metal layout, and the addition of a V_SS contact to each pixel for a reduction in color cross-talk.

Figure 1a: Samsung CIS Pixel BEOL (Filled Cavities); Figure 1b: MIM Capacitors

The Panasonic DMC-G1 was a noteworthy release, as it was the first in the Micro Four Thirds system, a “mirrorless DSLR format” created by Olympus and Panasonic. The aluminum BEOL used by the DMC-G1 pixels is shown in Figure 2a. The major knock on that first release was the absence of HD video function, a feature added for the second generation DMC-GH1. Upon receiving the DMC-GH1, we fully expected to see a fabrication process similar to the DMC-G1, but partnered with a new design to add HD video functionality. While still early in our analysis, we have been pleasantly surprised to see Panasonic switch fabs and radically re-design their fabrication process and pixel architecture. Figure 2b shows the four metal (one aluminum, three copper) BEOL used by the DMC-GH1. Additionally, Panasonic has moved away from their traditional LiveMOS architecture, which previously allowed them to implement their pixel wiring in a two metal BEOL process.   

Figure 2a: Panasonic First Gen. CIS (Al BEOL); Figure 2b: Second Gen. CIS (Al/Cu BEOL)

Clearly, the competition is on the move, so what about the bellwethers? We don’t have recent data points from Canon or Nikon in this class of DSLR, but Nikon has certainly brought innovation to its DSLRs simply by sourcing internally designed sensors instead of Sony’s. The first example of this, the D3, we suspect was fabbed by Renesas [5]. That device saw innovation in the form of selective pixel antireflection (AR) layers, dual microlenses, and substantial well and substrate engineering.

Canon seems to follow the “if it’s not broken, don’t fix it” philosophy. For example, Figures 3a and 3b show the pixel BEOL from the EOS 5D and EOS 5D Mark II, respectively [6, 7]. Essentially the same fabrication process was used on these two sensors, fabbed three years apart and used in markedly different classes of DSLR. Despite a modest evolution in pixel architecture, to date Canon’s pixel fabrication seems to be locked down, and we suspect Canon is getting significant performance gains from its Digic line of image processors.

Figure 3a: Canon EOS 5D CIS; Figure 3b: EOS 5D Mark II

In summary, we are seeing quite a lot of process innovation in reasonably priced DSLRs with HD functionality. This class of cameras is sure to be popular with consumers, and we fully expect to see innovation from the leaders as they are forced to defend their positions.  

References

[1] http://www.slashgear.com/two-big-continue-to-stomp-digital-slr-market-in-japan-3128291/

[2] http://www.photographyblog.com/news/cipa_predicts_falling_camera_sales_ in_2009/

[3] http://www.dpreview.com/reviews/specs/Pentax/pentax_k7.asp

[4] http://www.dpreview.com/reviews/specs/Panasonic/panasonic_dmcgh1.asp

[5] “Nikon 12.1 Mp CMOS Image Sensor from a D3 DSLR Camera with NC81338L Die Markings,” Chipworks, IPR-0710-801

[6] “Canon EOS 5D (706P) 12.8 Megapixel CMOS Image Sensor,” Chipworks, IPR-0511-802

[7] “Canon 1100 21.1 Mp, 6.4 µm Pixel Size Full Frame CMOS Image Sensor from the Canon EOS 5D Mark II Camera,” Chipworks, IPR-0811-801

Contrbuted by Ray Fontaine, Image Sensor Sector Analyst

Recently I had the pleasure of attending the 2009 IISW in Bergen, Norway, this past June 25 – 28.  

With a Backside Illumination (BSI) Symposium, three full days of paper presentations and invited talks, and a poster flash session, it turned into a marathon run-through the state of the art in digital imaging.

Silicon-based digital imaging is arguably one of the most challenging applications ever presented to the semiconductor industry.  For example, building a high quality camera phone module requires a multidisciplinary effort involving specialized wafer processing, circuit design, optics, and packaging.  Once the module is produced, it still has to interact with the systems level software and hardware.  In the case of consumer imaging, all of this effort is going towards building a camera system whose efficacy is far from objective.  How does one quantify a pleasing image?  Some consumers value an accurate reproduction of a scene, while others may appreciate images designed to skew reality in a favorable way.   The camera system designers of the world have a daunting task to say the least.  While innovation continues in all areas of digital imaging systems, nothing beats a high quality image sensor die.  In this light it is obvious to see why such a conference exists.  IISW serves as an incubator so that each can learn from the research of others, present new solutions to common problems, share ideas for the future, and reveal challenges in general.

The subject of small pixel design probably claims the highest visibility within the community.  Consumer small pixel imaging is currently in a transitional period as 1.75 µm pitch pixels make way for the 1.4 µm and below pixel generations.  The literature and real world examples indicate three choices on the menu as enablers for 1.4 µm pitch pixels:  BSI, optical waveguides (light pipes), and the inclusion of panchromatic pixels.  Marching any further down the pixel roadmap will almost certainly require a switch to BSI, as was nearly universally agreed upon during a straw poll taken during the IISW sessions.  The real question is when to deploy BSI?  BSI is not necessarily a silver bullet as it has its share of challenges.  Surface passivation schemes, wafer bonding techniques, and the choice of starting substrates (bulk vs. SOI) all conspire to add cost to the conventional CMOS image sensor flow, if there is such a thing.  Nevertheless, engineers always find a way.  Chipworks has reported on two of the leaders – Sony and OmniVision.  Sony chose to kick off the consumer BSI era with a 1.77 µm pixel pitch sensor, while OmniVision/TSMC went right to 1.4 µm for their first BSI outing. Nearly all of the other small pixel players (companies like Samsung, Aptina, Toshiba, and a dozen others), are in BSI development or will be forced there when their targeted applications demand it. What is sure is that these companies will find different ways to achieve the same ends; engineering departments will still play a role in product differentiation.

A single blog posting does not do justice to the breadth of work happening within the image sensor community.  Nor does it accurately capture the seemingly endless applications for all of these image sensors. For example, there was a very interesting slide of the eyeball of one unfortunate rabbit that was being used to study image sensor technology for the blind. The picture of the rabbit didn’t find its way into the final paper on retinal stimulation. But trust me it was amazing, hope-inspiring, and a little horrific.  As for the rest of the individual papers, the electronic versions will be posted online in December, according to the workshop website [1].  Finally, as a first time attendee to IISW I have to say there is a youthful enthusiasm in the image sensor community and a sense that (from a technological standpoint) much more, and maybe the best, is yet to come. 

[1] http://www.imagesensors.org/

The following is an excerpt from a blog published by Joff Wild, IAM Magazine, July 24, 2009

"I  have just heard the results of the first ICAP Ocean Tomo IP auction, held this afternoon in Chicago. According to the reports I have had, a total of just over $1.5 million was raised, excluding buyer and seller premiums. This is lower than any amount raised at any Ocean Tomo auction and is comfortably less than the approximately $2.75 million generated in San Francisco in March - which itself was seen as pretty disastrous. 

Characteristically quick off the mark, Terry Ludlow at Chipworks has been doing some number crunching. He has sent me a synopsis of how things panned out:

Today’s Ocean Tomo auction saw the smallest number of lots offered (29 versus the previous low of 40 at the first patent auction in April 2006), the smallest number of lots sold (4 versus 6 at last March’s auction in San Francisco), the smallest number of patents sold (12 US patents versus 23 last March), the smallest dollar value of an Ocean Tomo auction ($1,570,000 versus $2,659,000 in April 2006 – without 10% OT commission), but mid pack for average $ per patent at $130,833 the 6th largest of the 10 Ocean Tomo auctions held so far."

To read more, visit the IAM blog at http://www.iam-magazine.com/

The Latest iPhone certainly adds to the likelihood

With the new generation iPhone 3GS that was just announced Apple is trying to stay ahead of the pack for smartphones. The new feature that captured our eyes is the electronic compass (Also called a magnetometer.)  This is another example of a simple technology being elegantly applied to a software interface. We are interested to see whose device is used to realize the feature.  We will not have to wait long, the phones will be on sale June 19^th, and given past experience, we can expect to see the first teardowns within a few hours.

One of the leaders in this space is MEMSIC, who have been first to market with such a device, and is likely a forerunner to land this socket. At the risk of putting out false promotion for this company, we’ll say first that this commentary is about the interesting technology itself and not specifically about a design win. The target device discussed here is the Electronic Compass Board (ECB) evaluation module from MEMSIC (figure 1), and it contains both their novel thermal accelerometer and an electronic compass.

FIGURE 1: MEMSIC Eval Board

The creation of a MEMS magnet is almost a perfect example of elegant simplicity. Does anyone remember a book called, “101 Things a Boy Can Make” by author Arthur C Horth?  Somewhere, in the middle was a project for building an electromagnet using a screwdriver, some wire, and a battery. Many a young engineer did just such a project, for science class or to get a scout science badge. Well, MEMSIC certainly didn’t build something quite that simple, but its engineers must have has a touch of nostalgia in taking a simple concept to a whole new level to meet the complex demands of hand-held devices.

One of these is the need to have it detect the earth’s magnetic field, regardless of what direction the device is being carried or used, since most consumers would not tolerate an application that forces them to hold the compass perfectly still and level. To achieve this MEMSIC has used three sensor chips, and simply ‘bent’ the circuit board to achieve the 3^rd axis, as seen in figure 2. Pretty impressive, given the package is only 1.2mm thick.

FIGURE 2 - X-Ray of Magnetic Sensor

According to MEMSIC the magnetic sensors are anisotropic magnetoresistive (AMR) sensors.  They feature special resistors made of a permalloy thin film, which during manufacture are exposed to a strong magnetic field to orient the magnetic domains uni-directionally, establishing a magnetization vector.  An external field such as the earth’s makes the magnetization rotate, and this changes the film’s resistance.

The magnetoresistive sensors are arranged within a Wheatstone bridge circuit, so that the change in resistance is detected as a change in differential voltage, so that the strength of the applied magnetic field can be inferred.

A very strong external magnetic field could upset, or flip the polarity of the film, changing the sensor characteristics.  To allow for this a strong restoring magnetic field must be applied.  This is enabled on chip with a magnetically coupled strap.

For more information including die photos for the sensor and ASIC chip, registered readers can download our exploratory report. 

A compass feature combined with inertial sensors promises to improve the dead reckoning capabilities of mobile devices, and reduce the energy drain caused by GPS.  It will be very interesting to see what new apps the iPhone 3GS will have , now that it is enabled with a true eCompass.

For ordering information or any additional details about Chipworks reports and services please contact insidetechnology@chipworks.com

Apple Shuffle Non-DRM Chip Undressed

Contributed by Gary Tomkins

The new iPod shuffle has caused quite the “tempest in a teapot” over the last couple of weeks with the knowledge that the iPod contains no controls in the main body, only in the headphone cable. And standard headphones will not work with the iPod.

First off let me state . . . what a daft idea,  a sure way for most of us to avoid buying one! I say this as someone who loves his Macbook, an owner of four Macs (and a working version of the original Mac-only iPod, and Shuffle). I am probably regarded as a “Mac Fanboy” here at Chipworks. Steve Jobs what were you thinking? I am pretty sure when my current Shuffle dies, it will not be replaced by one of these . . . end of rant.

Anyway, back to the chip – the now infamous 8A83E3 (or 89S3E3 seen in some versions). Early speculation suggested that it was a DRM chip, which clearly would be a very, very bad thing. Fortunately this has been refuted by Apple, and it is just a proprietary control chip. Apparently part of a “made for iPod” licensing program that will incur additional charge to manufacturers wanting to make headphones for the iPod. So, it’s just a bad thing. Obviously some circuitry is required to control the iPod, and if you have no interface with the iPod, it has to be in the cable somewhere.

One long-shot rumour is that the chip actually contains a microphone. As Apple does sell headphones with microphones, it’s just possible that they are using the same device and activating the microphone through software. So I thought I would throw our labs at this part and take a peek at what is inside this chip.

Here is the black “Apple goodness” with the Apple headphones that I would typically throw out, as they don’t fit my ears.

The small board with the actual headphone wires passing through the controller.

Our chip is not the 8A83E3 or 89S3E3 that has been posted elsewhere; ours is the 8CT3E3. So we have an 8xx3E3. The 8xx is likely a date code or wafer identifier.

The packaging is actually pretty unusual. It is a chip-scale bare die assembly, where the die has an RDL (metal redistribution layer) and solder balls directly flip chipped to the board. The die marking is a laser marking on the back of the silicon die.

Here is the die “undressed.”

It’s a small, 1.35 mm x 0.85 mm, die made by Texas Instruments with die markings of CDPS3271C.

The die markings clarify the part number, which is actually a typical TI date code. The 8x represents the year and month, and the next four characters are the lot code. Therefore, our three parts were made in September ’08 (89), October ’08 (8A), and December ’08 (8C).

Taking a peek at it down the microscope, it looks like it is fabricated with a three metal BiCMOS process, likely 0.25 µm or 0.18 µm. There is not really a lot of circuitry on the die, but then again how much is really needed to relay the button commands to the processor chip – just the volume controller and the interface for the capacitative sensors on the back of the board.

So no DRM, no microphone; just a high volume design win for Texas Instruments.

CMOS Image Sensors in Camera Phones – Trending Towards a Commodity?

Contributed by Ray Fontaine, Process Analyst

The Image Sensors World blog’s anonymous author, who dutifully tracks the news of the image sensor community, has created a forum for readers to share their observations of current events. Recently, a few interesting comments have appeared regarding commoditization in the high volume, small pixel, consumer imaging space. Since Chipworks purchases several camera phones on a quarterly basis, it seems like a good idea to share some design win information we’ve gathered. Table 1 is a selection of camera phones added to our inventory within the last year or so. I withheld specifics since this information is typically something our clients hold privileged (contact us for more information). The high level design win data for the primary image sensor is listed for each. Note that this is neither an exhaustive list of camera phone manufacturers, nor is it a comprehensive list of the cameras in our database. This is a snapshot from which a few observations can be made.

Table 1: Selected Camera Phone Primary Image Sensor Design Wins (downstream model details withheld)

The obvious interpretation of this list is that there doesn’t seem to be any loyalty from phone makers to the image sensor groups within their own company. This is not unusual, as product managers have a mandate to source parts that are the best fit to their cost/performance/delivery requirements. Still it is interesting to see Samsung, for example, source imagers from their competition.

A new trend (for Chipworks) is finding identical model numbers of camera phones in which the image sensors have been sourced from two vendors. This is represented by the model numbers in bold, corresponding to RIM and Samsung having sourced their CMOS imagers from OmniVision/STMicroelectronics and Micron/Sony, respectively. The frequency of such behavior is difficult to gauge, as we usually only purchase one or two of a particular phone (unless we find something interesting and need more for full RE analysis). Perhaps by chance, these two instances have happened within the last month.  Two data points does not a trend make, but we expect to see more of this in the future. 

The design win story becomes even more interesting when vertically integrated phone company A (whom have a CIS catalog) source their primary camera from competitor B, and their secondary camera from yet another competitor! Arguably the secondary camera market is already commoditized, as witnessed by the problems the formerly dominant OmniVision is having in that market. It remains to be seen if Toshiba’s use of TSVs will give them an edge in that market space.

Is there a trend towards commoditization for imagers in camera phones? The answer is likely different depending on where the phone is positioned in the stratified camera phone market. For the average phone, the answer seems to be trending towards yes. Once the image sensor specifications are met, the phone manufacturers are happy to pit vendors against each other on pricing. Do consumers care? To some extent they do. And in writing this blog, I’ve found a nice camera phone comparison site at cnet. The question is which of the two possible image sensors was in that Samsung “Model A” phone they tested? : )

Since When Does a Resistor Become a Diode?

 Contributed by Jefferson Chua, Circuit Analysis Engineer

We have grown used to great fanfare about the material composition in the tiniest feature of a transistor design, but circuit designers often become jaded about the very innovation that they are designing. They are so entrenched in the details that they never get to see the big picture. "Ho hum, another polysilicon resistor."

But occasionally, even we get surprised.  In this case, a resistor that is actually a diode. Everybody on our circuit RE team was perplexed about this component because planar investigation clearly showed that it was a resistor, yet circuit analysis-wise, it should have been a diode. The circuit just did not make sense.

The TT3040AS chip, found on the Sonion TC100Z21A silicon condenser was analyzed. One of the blocks analyzed was the device’s VPP pump.

The VPP pump circuit is suppose to be classified as a typical Dickson-type charge pump Yet, no diodes were present in the circuit.

To uncover what was really happening required a SEM cross section of every component in the VPP pump. Usually, we only need cross sectioning to determine material composition for delayering purposes, not for circuit extraction – so this was a little new to us. The first component analyzed was the capacitor. The capacitors were found to be really capacitors, and are classified as PIP caps (polysilicon-insulator-polysilicon).

The next component on the hot seat was the suspected “resistors,” having an area of five squares. From the cross section shown below, we confirmed our suspicions that the component we had initially identified as a polysilicon resistor is actually a polysilicon wire doped with P⁺ on the left side and N⁺ doped on the right side, forming an N-P diode.

So there you have it. The lesson is that when normal evidence shows unwaveringly something doesn’t quite make sense, you need to dig a little deeper. The people over at (CSI Miami/Bones/Dexter/choose your favorite crime show) would be proud.

Speed vs leakage in the TSMC 40 nm process - Looking forward to the latest in advanced CMOS technology

contributed by Dick James

Last May, Altera launched their new Stratix IV FPGA family, fabricated in TSMC’s 40 nm process; in December they announced the first product shipments. TSMC had initially offered a 45 nm process, but last year they confirmed that they would go straight into a 10% shrink, and make the 40 nm platform their main production technology.

To quote their 40/45 nm brochure, “TSMC's 40 nm General Purpose (40G, also known as 45GS) process is positioned as a full-node technology, although using half-node design rules, with IP ecosystem support. It provides 2.35 times the standard cell raw gate density of the 65 nm process. TSMC's 40 nm Low Power process (40LP) is also supported with a comprehensive IP infrastructure.” The SRAM cell size is claimed as 0.24 µm², which will make it the smallest that we have ever seen – the Panasonic and Intel 45 nm cell sizes were 0.38 and 0.34 µm², respectively.

Chipworks has obtained some of the latest 40 nm Stratix IV parts, and will be analyzing them to see what TSMC’s 40 nm product looks like. 

What can we expect? It has become clear that Intel is likely to be the only company to use high-k/metal gate at the 45 nm node, so we expect a conventional gate dielectric (almost certainly nitrided), and at best in the 1.2 – 1.5 nm thickness range. The TSMC brochure claims a triple gate oxide option, so to keep leakage at a minimum, it is likely that the thinnest dielectric will only be used for the most critical transistors, maybe 5% of the total count, even with the highest performance product.

However, according to the FPGA Journal, “Altera claims to have compromised on speed at the transistor level in order to reduce leakage. These compromises include increasing Vt, increasing channel lengths, thickening gate oxide, and decreasing Vcc. Next, they worked to gain back enough of that speed via other means to assure that Stratix IV is still faster than its predecessor (65 nm Stratix III). Altera says the net result is that Stratix IV has an average of 30% lower total power consumption compared with similar designs on Stratix III.”

So our Altera transistors may not use the thinnest gate dielectric (t_ox) or the shortest gate length – perhaps a 45 nm gate length and ~2 nm t_ox, as used in the TSMC 55 nm half-node AMD/ATI chip that we analyzed last year. 

However, there are other ways of increasing transistor performance – we have seen limited use of strain techniques from TSMC so far, especially on PMOS devices, so we are likely to see something new there.

TSMC presented a 45-nm process at IEDM 2007[1], with possibly a few clues – dual stress liners with both tensile and compressive contact etch-stop layers are reported.  NMOS is further enhanced by stress memorization, and PMOS by embedded SiGe and the use of (110) orientation wafers.

The other factor in chip speed these days is the metal dielectric stack, perhaps a more important determinant than transistor speed. TSMC’s 40/45 nm processes are claimed to use extreme low-k dielectric material (Black Diamond II?) in the first seven metal layers of an 11 metal stack. 

If that is the case, this will only be the second part that we have seen with second generation low-k. The other was a Via Nano, fabbed by Fujitsu in their 65-nm process, using their Nano-Clustering Silica technology.

Chipworks will be performing both a structural analysis and transistor characterization on the Altera Stratix IV in the next few weeks – stay tuned!

[1]           K-L. Cheng et al., A Highly Scaled, High Performance 45nm Bulk Logic CMOS Technology with 0.242 μm2 SRAM Cell, Proc. IEDM 2007, pp. 243 - 246

Canon's Shifting Approach to Compact Camera Sensors

Contributed by Ray Fontaine

It is not front page news to say that CCDs continue to be replaced by integrated system-on-chip (iSoC) CMOS image sensors (CIS) in consumer applications. However, the global market share is still large for CCD imagers, and they have resisted being replaced by CMOS imagers in certain applications.

According to iSuppli's market share numbers in 2007, CISs held their lead, with CCDs a relatively close second. The iSuppli numbers include all imaging devices, so the CCD market share is buoyed by high volume commercial applications such as copiers, scanners, and medical equipment. Interestingly enough, while the 2007 image sensor market experienced respectable growth, CCDs enjoyed a higher growth rate than the CIS market. 

Typically, the imagers that we analyze are targeted at high volume consumer electronic devices. In this market space, there is a clear view of the CCD vs CIS market share, provided you factor in the application. Camera phone and DSLR companies abandoned CCDs some time ago in favor of CMOS imaging chips, with their superior performance and ability to add logic and memory functionality to the die.

One application where CCDs have thrived, even in recent times, is in digital still cameras (DSC). In fact, if you go to your local electronics store to buy a DSC, you might be more likely to bring home a CCD than a CIS. The tide may finally be turning though, as discussed in a recent Tech-On! article [1]. Canon announced the start of production of a 1.7 µm pixel size CIS to be mounted in their PowerShot SX1 IS camera [2]. Canon, who have traditionally used only CCDs for their DSCs, are positioning this new PowerShot camera in the "high-end" DSC market. The article also suggests that Canon is "highly likely" to use in-house CIS for almost all of their DSCs. This reasoning is linked to consumer demand for full HD video and high-speed burst shooting in a DSC. Canon have long been in the CIS game, having made CIS sensors for their own DSLRs and video cameras. So perhaps it is natural for them to want to source their point and shoot sensors internally.

We've just completed a process analysis [3] of the CIS from the SX1 IS camera and found some truly innovative features. Figure 1 shows the image sensor assembly from the SX1 IS, including the LC1090A imager mounted to a copper frame, and a Texas Instruments/Burr Brown VSP7700 front end image processor. This assembly is connected to the camera main board, which is home to a package-on-package (PoP) assembly shown in Figure 2. 

Figure 1 – Image Sensor Assembly from SX1 IS

Figure 2 shows the top chip of the PoP, an Elpida part which itself is a multichip package (MCP) containing one Elpida die and one STMicroelectronics die. A Canon Digic 4 processor is flip-chip mounted to a fiberglass board beneath the Elpida package. With all of this horsepower, the SX1 IS is poised to make a big splash in the cross-over compact camera space.

Figure 2 – Elpida HB0030A16C and Canon Digic 4 Package-on-Package (PoP)

The LC1090 CIS represents a fundamental shift by Canon in its approach to wafer fabrication. This is the first time we have seen them use a copper back end of line (BEOL) process in an imager. They haven't used light pipes, but instead added process steps to clear the line sealants from the optical path. Compared to previously analyzed Canon image sensors, their pixel design can safely be called revolutionary. The signal routing metal has been fully optimized for optical symmetry, and borderless contacts are used as part of a space saving layout. For us process types, the biggest story has to be the use of Dow Chemical's SiLK low-k dielectric in the BEOL.

Figure 3 shows a low magnification TEM view of the pixel BEOL. The use of SiLK marks the first implementation of a true low-k dielectric in the BEOL of an image sensor (based on Chipworks' analyses). The low-k resin is likely first generation SiLK D or SiLK J, as opposed to Dow's next generation porous SiLK. First generation SiLK has a reported k-value of 2.6 [4]. Note that the line sealant dielectric has been cleared over the photocathodes.

Figure 3 – TEM Cross Section of Canon LC1090 Pixels

Figure 4 shows a TEM of a Lattice Semiconductor FPGA fabbed by Fujitsu. This part, analyzed in 2005, was the first part we found that used SiLK [5]. Upon checking the Lattice Semi report for comparison, we noticed that the copper metal part of the BEOL was identical to our Canon part. So, this part might be fabricated in one of Canon's newest fabs. But, we also consider whether Fujitsu was involved in fabricating the Canon image sensor. A hybrid fabrication process is used for the Canon LC1090. The FEOL is typical of Canon 0.25 µm generation processing. The BEOL is consistent with a 0.13 µm process on 200 mm wafers. 

Well of course this is just speculation, but it is possible that Canon processed the wafers up to the transistors, and shipped them to Fujitsu to perform the copper processing. We've seen conventional CMOS fabs behave in this way; Texas Instruments built one of their 65 nm parts up to the transistor level, and shipped it off to TSMC to finish the BEOL. If this were true with the Canon part, they likely finished the wafer processing themselves with the final aluminum and passivation, and the addition of the color filter and microlens arrays. An early analysis of the Digic 4 processor indicates that it was fabricated by Fujitsu in their 65 nm process, so perhaps Fujitsu has partnered with Canon to help them come up to speed with their copper CIS process. Let me repeat the part about this being speculation!

The Digic 4 process is in itself a story, since it is the first production process we've seen that uses second generation low-k dielectric material! We have also seen this in the Via Nano low-power microprocessor, also fabbed by Fujitsu.

Figure 4 – Fujitsu 130 nm SiLK Low-k Dielectric Process

Getting back to the LC1090 CIS, according to the Tech-On! article [1], Canon have typically sourced their DSC imagers from others, including Sony. So, does this signal a changing of the guard for compact cameras in general? Mobile, small form factor applications led the way in CIS migration, and that was soon followed by DSLRs and video cameras. It begs the question: for how many more years will we find CCDs living in our gadgets?

References

[1] http://techon.nikkeibp.co.jp/english/NEWS_EN/20080919/158225/ 

[2] http://www.dpreview.com/reviews/specs/Canon/canon_sx1is.asp

[3] "Canon LC1090A 10.0 Mp, 1.7 µm Pixel Size CMOS Image Sensor Featuring SiLK Low-k Dielectric," Chipworks report, IPR-0811-801 

[4] http://www.dow.com/silk/lit/ 

[5] "Lattice Semiconductor LFEC1E FPGA Fujitsu SiLK Process Review," Chipworks report, SAR-0510-801 

Contributed by: St.J. Dixon-Warren

One of the more mature, if atypical, applications of MEMS technology is in image projection. Texas Instruments has pioneered the use of MEMS techniques to create its digital light processor (DLP) device, and stayed with it so that DLP projectors now have more than half the projector market share.  A couple of years ago TI started talking about miniaturized pico-projectors that could be fitted into a jacket pocket and hooked up to a mobile phone, and last year a two or three models actually made it to commercial production.

The latest pico-projectors combine novel use of light, lens, and silicon making them particularly interesting. Chipworks recently procured an Optoma PK101 pocket projector and inside we found a Texas Instrument digital-mirror device (DMD) that featured a 3.81 mm x 2.65 mm pixel array, with a 7.5 µm square pixel size - the smallest size that we have seen from TI to date. The device itself  makes clever use of three light-emitting diode light sources to project a full color image.

Texas Instruments announced the technology at the 2009 International Consumer Electronics Show (CES) calling it, “digital light projector (DLP) technology that enables a new generation of ultra-portable pico-projectors with adoption in a wide range of products,” including the Optoma PK101. According to Yole Developpements, Texas Instruments’ DMD technology represents one of the largest MEMS sectors. In 2007, TI was ranked second in overall MEMS manufacturing worldwide, with sales of US $800M for their DMD business.

The Optoma PK101 is a 50 mm x 103 mm x 15 mm thick miniature projector, as shown in Figure 1. The inside of the PK101 is shown in Figure 2. The DMD projector module is located at the left end of the device. A bank of three diodes, for red, green and blue, are located along the top edge of the module.

The DMD module was removed from the projector casing and the top lid was removed to expose the interior of the module (Figure 3). A pair of lenses projects the diode illumination onto three dichroic mirrors, one for each of the three colors.  These three mirrors combine the three colors and project them onto a fly’s-eye lens. This fly’s-eye lens diffuses the light, which is projected on to a tilted mirror that reflects the light onto the DMD micro-mirror array. Operation of the device depends on synchronous modulation of the three diodes in conjunction with the micro-mirror array of the DMD chip.

The resulting three-color image is projected by the DMD chip through a lens column, shown on the right side of the front of the DMD module.

At the moment it is unclear whether the packaging of the 15.5 mm x 9.0 mm DMD device (Figure 5 and 6) is a smaller version of the wafer-level package used for the S1076-6318W device, but using a ceramic substrate, or a lower cost plastic version of the die-level package used for the  S1076-7402, analyzed by Chipworks in 2005.

The PK101 pixel array (Figure 7) is also markedly smaller than the two previously analyzed devices at 3.81 mm x 2.65 mm. This versus 10.7 mm x 14.2 mm for S1076-7402 and 8.5 mm x 11.3 mm for the S1076-6318W. The 7.5 µm PK101 pixel size (Figure 8) is 41% and 25% smaller than the S1076-7402 and S1076-6318W, respectively. The SRAM circuit used to latch the DMD micro-mirrors will have been shrunk by a corresponding amount for this new Texas Instruments DMD device. The ~500 pixel x ~350 pixel array is consistent with the HVGA specifications.

The Optoma PK101 is evidence of Texas Instruments’ continued innovation in the DMD market space. The portable market has required the adoption of lower cost plastic packaging, plus the design and manufacture of a smaller footprint DMD module. As our analysis continues, it will be interesting to see how they have modified the electronic and mechanical components underneath the micromirrors to work with the smaller footprint and 5-volt battery power supply.

Last week I was at the IEDM conference, held in San Francisco, and unfortunately close to the Christmas holidays.  This may have been a factor in the reduced attendance this year, down to ~1600 from ~2000 last time on the west coast, although current economic circumstances are the more likely cause.  The number of papers was also down, to just over 200, and out of that number there were a few suspended papers due to lack of a speaker.

I had been asked by the guys at Solid State Technology magazine to craft a few paragraphs each day giving my impressions of the most interesting papers that I attended, so rather than re-write a conference review, the collected version is below.  I may give a more detailed commentary after going through the papers at more leisure, but that will not be until the New Year.

In the meantime, Chipworks will be closed for the Christmas break until January 5, 2009.

Happy holidays!

IEDM Day 1: Dense data on 22nm

Dec. 15, 2008 - Sunday at IEDM is always short course day, and this year's two topics were on "22nm CMOS Technology" and "More than Moore: Technologies for Functional Diversification." One of the courses is usually a focus on potential technologies for a couple of process generations ahead (e.g., 22nm). This is perhaps looking a bit far ahead, since 45nm is hardly well established yet; Intel and Panasonic have been the only two players until AMD's recent entrance.

I took in the 22nm course, although there were a couple of sessions in the other I would like to have been at -- Tom Lee and Albert Theuwissen are both entertaining speakers, and their respective perorations on RF/analog and CMOS imaging (both pretty hot market segments at the moment) would have been interesting.

The 22nm course was kicked off by the ever-genial Hiroshi Iwai, with a run-through of technology scaling through the lens of the 2008 ITRS. In essence, he detailed the changes to the 2008 update (due out at year's end), in particular reflecting the slowing rate of scaling that we have seen in recent years, so that at 22nm V_dd, gate length, EOT, and xj will all be larger than predicted in the last ITRS. Correspondingly, the life of bulk CMOS and the adoption of multi-gate devices (MuGFETs) has been pushed out by eight years. And of course the k-value of interlevel dielectrics has slipped again -- a bit ironic, since we have just found our first 2nd-gen low-k part using Fujitsu's nano-clustering silica with a claimed k of ~2.25, putting them ahead of the ITRS prediction.

Iwai finished his talk with his personal roadmap of technologies beyond CMOS, with Si nanowires and germanium or III-V channel MOSFETs being the short-term prospects, and carbon nanotubes, graphene, and other prospects out "in the clouds". Nanowires are his preference, because of better short-channel effects.

Next up was Kelin Kuhn of Intel, who gave the most amazing review of the challenges in achieving manufacturable 22nm from the device perspective -- a hundred densely packed slides in an hour with well over a hundred references. She described the problems caused by increased resistance (SDE and silicides) and fringe capacitances, gave a detailed explanation of mobility and orientation effects, and discussed high-k/metal gate methodology and the pros and cons of planar CMOS vs. MuGFETs/FinFETs. She made one point about MuGFETs that hadn't occurred to me -- essentially they are quantised transistors, since larger transistors have to be made from many units of a single gate crossing the fin substrate, so a whole different modeling regime applies before you even get into the design cycle. At the end of this avalanche of information, Kuhn summarized by saying that 22nm is likely to be planar, evolved from current technology. MuGFETs won't happen soon; there are just too many risks involved for them to become real in the next five years.

After lunch, Geert Vandenberghe from IMEC discussed the lithography options, covering wet lithography and EUV and the associated problems with mask and reticle design and manufacture. He also went through the different types of double masking and patterning -- although strangely absent was the subtractive double patterning practiced by Intel, in which gates are first patterned as continuous parallel lines and then cut into dummy and functional segments by a second etch mask.

Jeff Gambino of IBM gave a good overview of the BEOL challenges, taking it beyond the usual problems with super-narrow lines and super-fragile low-k dielectrics, also discussing air-gap techniques, packaging including TSVs, and reliability problems.

Finally, Purdue University's erudite academic Kaushik Roy reviewed device and circuit interactions. The inherent variability of processing and structures at nodes 45nm and below can make device operation unpredictable, never mind the increased leakage. He detailed some of the circuit techniques used to mitigate the problems, such as high- and low-V_t transistors, gated blocks of memory, and the like. Some of them have been around for a while, but the need at 22nm becomes even greater. Judging by some of his slides, he's been working with Intel, and the comments on dual-V_t made me wonder if his work had an input into Intel's SoC/Dual V_t paper to be presented on Wednesday.

By that end of the afternoon we were getting punch-drunk with an excess of information, but all in all, a good and informative day. I do have some criticism for the facility side of the course -- too many of us crowded into too small a space, I gather there were over 300 attendees -- and the coffee ran out! Not quite as bad as sitting in a full 747, but getting there.

For my money, Kelin Kuhn gets the Data Density of the Day award (definitely not a criticism); hers was an extremely well-structured talk, though most people would have taken a full morning to deliver it! Now for the conference proper.

IEDM Day 2: Brain cells, "stress," nanowire batteries

It's hard to discuss the Monday morning plenary sessions without getting a bit linear. First up was Peter Fromherz from the Max Planck Biochemistry Institute in Munich, talking about interfacing chips with brain cells. That sort of topic usually makes my eyes roll up, but he actually had some good pragmatic stuff. Question: How do you monitor brain cells without affecting them? Answer: Lay them on a transistor gate so that the voltage pulses turn the transistor on, and measure the response.

Similarly, to put a voltage pulse into a cell without contaminating it, you lay it on a capacitor with a physiologically inert HfO₂ or TiO₂ dielectric, and pulse the capacitor. The actual link between the cell and the inorganic devices relies on the response of the ions within the electrolyte containing the cell and device, influencing the ion channels that are the communication media of nerve cells. All the semiconductors have a passivation layer so that the electrolyte does not affect the chips.

Fromherz had an impressive video of a slice of brain laid over an array of transistors, showing how a pulse at one point influenced the neurons and was transmitted through the tissue, its movement monitored by the transistor array. A bit simplistic -- as well as a bit gruesome -- but a good example of how basic research could lead to the prosthetics of the future. The blind may yet see, if this kind of experiment pays off.

Stefan Lai, formerly of Intel, then Ovonyx, and now independent, gave a review of non-volatile memories, working his way through NOR and NAND flash to cross-point memories such as the SanDisk/Matrix, to his recent phase-change memories and IBM's Millipede MEMS-based system. Asked when PCM would appear in a real product, he declined to comment -- but given the list of pros and cons (mostly cons) for PCM he had shown earlier, it doesn't look any time soon.

As the session stretched into numb-bum time (there are no morning or afternoon breaks at IEDM, and three hours is a long time to sit in a conference room), Tatsuo Saga of Sharp gave a good review of the PV options (though at times a little sales-pitchy and promotional). One surprising stat: some of the more complex solar cells are now closing in on 40% conversion efficiency.

Having just installed geothermal heating at home, he had me thinking about solar PV as well -- not an obvious thing for Canada where I live, but Ottawa is actually south of a lot of the installations in Germany, which has gone gung-ho for renewable energy of all sorts. Unfortunately, now that fossil fuel prices have fallen off a cliff, the economics have changed and the payback time will be a lot longer -- exactly what torpedoed the solar movement back in the '80s.

On the way out of the hall for lunch I crossed paths with Stanley Wolf, author of what is still the most comprehensive set of reference books for the industry, "Silicon Processing for the VLSI Era" -- now a slightly quaint title, since time has gone by since they were first launched. I mention this because Stan is thinking of updating volume 1, last revised in 2000, and needless to say quite a lot has happened since then in chip processing. Keep an eye on his Lattice Press Web site to see when the new version comes up.

Afternoon sessions

The conference proper started in the afternoon with the usual irritating plethora of parallel sessions. The AMD/IBM/Freescale alliance gave a paper on embedded carbon-doped epitaxial source/drains to stress nMOS transistors (paper 3.1), which gave a decent 9% I_on increase over the equivalent device using nitride + memorized stress. Unfortunately good epi growth requires low-doped drain extensions, so there is still work to do to get the technique integrated, increased series resistance is not a price we want to pay.

This was followed (3.2) by an examination by Fujitsu of the mechanism of the stress memorization techniques (SMT). The gate polysilicon is amorphized by implantation, then capped with nitride. During the source/drain anneal the amorphized silicon expands as it re-crystallizes, but since it is constrained by the cap and sidewall spacers (SWS), compressive vertical stress is applied to the channel underneath. After the anneal the nitride cap is removed, and a conventional contact etch-stop liner (CESL) used to apply lateral tensile stress. We tend to think of nMOS stress as only needing to be tensile, but in the z-direction it's compressive stress that helps for both nMOS and pMOS.

Figure 1: Effect of channel stress on nMOS & pMOS transistors. [1]

As part of the investigation, arsenic and phosphorus source/drain implants were tried, and oxide and nitride sidewall spacers. As would be expected, the harder nitride SWS is more effective at applying stress to the channel, and possibly the greater atomic mass of the arsenic increases the expansion tendency of the gate polysilicon.

Figure 2: Effect of SMT on electron mobility. [2]

Then we got into one of those timing clashes that IEDM is notorious for -- two interesting papers in different sessions at the same time! Both by Intel, as it happened, one on CMP and the other on the use of (110) silicon -- I picked CMP, since the Intel 45nm metal gate structure would not have been manufacturable without a highly tuned CMP capability.

That was the message from Joe Steigerwald (2.4), and it jives with our analysis when we looked at the structure. CMP is used to polish back the surrounding dielectric to expose the sacrificial poly gates (POP step), to polish down the final metal fill and electrically isolate the metal gates, and of course for all the copper levels in the BEOL. This is complicated, and arguably helped, by the density of the real and dummy gates -- see our pictures below.

Figures 3-4: Intel's metal gates in cross-section and plan-view. (Source: Chipworks) 

If you look at the structure, we can see that under-polish at the POP step will not expose the poly for removal, and over-polish could get into the raised epi pMOS source/drains. Similarly under-polish at the metal removal could leave gates shorted together, and affect the contact etch yield, and over-polish will leave them too thin and high-resistance, especially pMOS if too much of the Al-Ti fill is removed. One thing not mentioned is the thin layer of AlTiO on the top of the gates, presumably a side-effect of the CMP -- or are they using E-CMP (electrochemical CMP)?

The standing-room only paper of the afternoon was an invited paper given by Yi Cui of Stanford, on nanowire batteries -- they are doing some really interesting work on using silicon nanowires to replace graphite as the anode in lithium-ion batteries. Bulk silicon has good performance, but limited surface area, and expands too much as charge is stored to be a practical device. With nanowires there is of course much greater surface area, and room for the nanowires to expand. The bottom line is that there is potentially as much as ten times as much charge storage capacity as the equivalent conventional Li-ion battery. They are also working on LiMn₂O₄ nanorods to improve cathode performance, and getting encouraging results. After the plenary session on solar, which requires the extensive use of batteries if you want to go off-grid, this paper appeared to strike a chord with attendees; there was great enthusiasm for this work.

In the evening was the reception, a good chance to catch up with colleagues, and confirm that engineers and scientists are the same as normal folks -- give them food and wine, and you need ear protection after a while!

[1]  S. Thompson, et al, “A 90-nm logic technology featuring strained-silicon; IEEE Transactions on Electron Devices; Volume 51, Issue 11, Nov. 2004, pp. 1790 -- 1797.

[2]  T. Miyashita et al, “Physical and Electrical Analysis of the Stress Memorization Technique (SMT) using Poly Gates and its Optimization for Beyond 45nm High Performance Applications,” Proc. IEDM 2008, pp. 55-58.

IEDM Day 3: SRAMs, image sensors, flash memory

Dec. 17. 2008 - Today was a bit of a researchy day, with a predominance of more academic or blue-sky papers. Consequently I tended to bounce around a bit without a real focus, everything from SRAM to image sensors to radiation soft errors in flash memories.

The IBM Common Platform group started the day (paper 10.1) with a 32nm high-k/ metal gate SRAM paper, actually a scaling study that went under the radar of the conference pre-publicity of dueling 32nm SRAM sizing. IBM's Wednesday paper details a 0.157μm² cell, TSMC has a 0.15μm² cell, and Intel a 0.171μm² cell.

Here we have an analysis of a series of 0.149μm², 0.139μm², and 0.124μm² cells, fabbed in a low-power process with double patterning for gate and double masking for contacts. The HK/MG gives a reduction in the effect of random dopant fluctuation which decreases threshold voltage mismatch, and also drops gate leakage, enabling functional SRAMs down to 0.124μm². Adding a dual ground to the cell write assist also improves the voltage range and soft fail rate of the smallest cell, at what space penalty is not disclosed.

Chipworks has been focusing on image sensors for a while now, so Rohm's announcement of a CIGS on CMOS sensor (paper 11.2) caught my attention. CIGS (copper indium gallium selenide) is one of the hot materials in the PV field, so the idea of using it for an image sensor is not that far off the wall -- the big problem has been high dark current.

Rohm gets around this by using a double layer of zinc oxide as the top blanket electrode. One layer is semi-insulating ZnO, and the top sub-layer is Al-doped to give conductivity; this has the dual advantage of isolating the pixels and reducing dark current. The CIGS is co-evaporated on to a molybdenum base layer/back contact (which contacts the top metal layer of the CMOS scanning chip below), with a CdS buffer layer under the ZnO bi-layer.

Figure 1: CIGS photodiode structure. (Source: Rohm) 

Figure 2: CIGS image sensor structure. (Source: Rohm) 

The pixels are 10μm × 10μm in a 352 × 288 array, so this is clearly a proof of concept. The sensitivity can be extended to sub-lux illumination levels by biasing the photodiode to induce avalanche multiplication. Since the photodiodes are on top of the die, they have an aperture ratio close to 100%, and this coupled with the CIGS spectral response extending into the near-infra-red makes the sensor suitable for automotive and security applications.

In the same session Samsung compared 1.4μm frontside- and backside-illuminated (BSI) sensors (paper 11.4). BSI sensors have been getting publicity of late, since the continuous drive for multi-mega-pixel phone cameras have driven pixel size down to the point where it's difficult to get enough light in to a frontside pixel. If you thin the wafer down so that the photodiode can go on the backside, then the aperture ratio is not limited by the metal stack on the front.

Figure 3: Frontside (left) and backside illuminated sensor structures. (Source: Samsung) 

As expected, the BSI sensor had impressive performance compared with the frontside version, and Samsung claims that the technology will extend pixel size down to ~1μm. I guess that will give us the dubious (for me) societal benefit of a 10-megapixel cameraphone.

By coincidence, we at Chipworks are now examining Sony's 1.4μm-pixel, 8-Mp chip -- I'll have to compare them when I get back to the office!

Another interesting paper (14.6) by Numonyx and a bunch of European universities discussed a joint study on potential neutron-induced soft errors in flash memories. They took a number of 4GB and 8GB chips and irradiated them to induce loss of data.

And neutrons do create data loss -- not necessarily at the level where it cannot be corrected by the built-in ECC that's on every chip -- but the trend is in the wrong direction, since denser memories and smaller feature size have higher data loss. This made me think of the latest flash memories that we have looked at, with a BPSG interline dielectric in them. Boron has a high neutron cross-section, so any chip with BPSG in it is a bit more vulnerable to neutron-induced soft errors.

Figure 4: TEM cross-section of storage cells in 8GB flash memory. (Source: Chipworks) 

Having said that, the statistics shown in the paper indicate that for every GB in the chips they tested, you may lose up to 60 bits if you spend 27 years at airline cruising altitude, depending on which flash chip you've got in your thumb drive. Given that these things are used for dumb storage anyway, will you actually notice 60 bits missing from that 8MB picture in your phone? All the same, a nice piece of research.

Renesas had a paper (18.1) that will have me bugging our TEM guys back in the office, since they've been mapping transistor strain using the acronym-laden LAADF-STEM technique (low-angle annular dark field scanning transmission electron microscope). This actually looks as though it might work, but you have to be able to do convergent beam and have the LAADF detector, and use a thick ~2500A sample.

Wednesday is the heavy stuff at IEDM -- multiple papers on 22nm, 32nm, 40nm, and 45nm from the big guys. More tomorrow!

IEDM Day 4: Sub-45nm roundup

 Dec. 18. 2008 - The morning was an endurance test, with nine consecutive papers on 22, 32, and 45nm devices. A lot of strained silicon, and not a few strained attendees! So it's a bit tedious, but rather than cherry-pick, let's run through the list from Session 27:

27.1
The IBM Alliance kicked off the day again with the 0.1 μm² SRAM cell that was announced back in the fall, fabbed at the Albany Nanofab. With a 90nm contacted gate pitch and gate length of 25nm, a suite of different techniques were used to create the test chips.

Not least the wet lithography; the active SOI areas were patterned using crossed quadrupole illumination; the gates used double exposure, double etch (DEDE, or DE2, or LELE -- acronyms are taking over again) with dipole illumination; the contacts used DE2 with a tri-layer resist; and M1 was patterned with double masking using dipole illumination and a single etch.

Other process elements are 45nm thin SOI, dual high-k metal gates (HK+MG), co-implants at the SDE/halo, and copper contacts with Ru liners. As this was a proof-of-concept exercise, stress techniques were not used, although in answer to a question the presenter implied that they were being introduced.

27.2
Next up was TSMC with a 32nm gate-first HK+MG process, with a 9Å EOT, 30nm Lg and 130nm contacted gate pitch, with an SRAM cell size of 0.15 μm². The usual suite of stress tools was used, SMT, e-SiGe, and dual stress liners (DSL), and junction profiles were optimized with co-implants. The BEOL has ten layers of copper, and 2nd generation low-k dielectric (k~2.55) at the lower levels (Black Diamond 2?).

27.3
IBM were back up again, this time the Common Platform et al, with a 32nm, single gate-first HK+MG bulk technology with 126nm contacted gate pitch and 0.157 μm² SRAM cell. The usual stress trio of SMT+DSL+e-SiGe is present, and thin-barrier copper with ELK (extreme low-k, k~2.4) in the BEOL.

27.4
Intel's turn this time, with tweaks to their 45nm process to add low-power and RF/mixed signal elements to the designer toolbox. After running through the base process, we had a shopping list of new features. Some were obvious -- the super-thick 8μm redistribution layer is ideal for inductors, for example -- but others need new process modules.

High voltage I/O transistors with a thicker SiO₂ layer have been added, as have low-power transistors with slightly longer gate lengths and tuned S/Ds to reduce junction leakage (co-implants?). Add in capacitors, varactors, one-time programmable fuses, and RF transistors and you have quite a shopping bag. At the end of the paper someone asked if there were poly devices (the replacement gate has not been replaced), which was met by the usual stony "I can't answer that" response -- which makes us all think that it's at least being looked. I must admit that at Chipworks we have thought about that possibility, at least for fuses.

Figure 1: TEMs of nMOS and pMOS logic (left top/bottom) and I/O transistors (right top/bottom). Note the thicker oxide layer in I/O devices. (Source: Intel) 

27.5
Now the NEC/Toshiba consortium; a 40nm high-k dielectric (but not metal gate) technology, with 40nm gate length, 168nm contacted gate pitch, 0.195μm² SRAM cell, and a thicker EOT of 1.75nm. A couple of years ago NEC announced a 55nm process with a hafnium-based gate dielectric, and it looks like this is a shrink.

They went into quite a lot of detail about the source/drain engineering, reducing junction leakage by using a Ge + N pre-amorphization implant before the SDE and halo implants, and putting a lot of work into the activation anneal sequence to co-optimize it with the SMT stress application (nitride stress is also used, no mention of DSL).

The gate litho is single exposure to keep costs down, and the BEOL has the choice of low-k dielectric, k~2.75 or 2.55, depending on cost requirement (Black Diamond 1 or 2?). This paper is worth going through in detail, as it discusses stuff usually described with a phrase or two.

Figure 2: 40nm transistors with HfO dielectric. Note the lack of thick dark metal layer. (Source: NEC/Toshiba) 

27.6, 27.7
I took a pass on these -- I needed a break!

27.8
Now we're into the late news papers -- NEC/Toshiba again, but 32nm this time, again with a cost conscious emphasis -- the target was to reduce per-function cost by 50% from the 45nm node. They claimed that this was achieved with a standard cell gate density of 3650K gates/mm²; it sounds impressive!

They achieve this by using single-pass lithography and gate-first HK+MG transistors. Contacted gate pitch is 120nm, and SRAM cell size is 0.124μm², but no other details were available. By the litho images below, it looks like the full suite of OPC and dipole/quadrupole illumination tricks is being used.

Figure 3: [Top] 0.124 μm² SRAM cell, (A) gates, (B) contacts, (C) Metal 1. [Bottom] D-type flip-flop, (left) active area, gates, and contacts, (right) Metal 1. (Source: NEC/Toshiba) 

27.9
This was the Intel 32nm paper that got the pre-publicity back in the fall. EOT is down a smidge to 9Å, gate length is 30nm, SRAM cell 0.171μm², we have 4th-generation strain, and the BEOL is 9 metal levels with slight tweaks to the low-k package, but still low-k/SiCN.

It struck me when we took apart the 45nm part that the technology had legs, and was scalable to 32nm; I think what we're seeing here is essentially a shrink (except, of course, with wet litho); we'll find out at the backend of next year when the chips appear on the market.

So as you can see the morning session was very intense, and there were other papers in other sessions that I wanted to get to. In the afternoon, session 37 was more focused on source/drain engineering, so I wound down by sitting on a couple of those.

37.2
Samsung has been trying out different co-implants and anneal cycles on their 45nm base process. Ge is used as a pre-amorphization implant before both n- and pMOS SDE and halo implants, and this was modified to Ge + C or F, and cluster carbon (C₁₆H₁₀) was tried to replace both.

In nMOS the cluster-C seems to give the best results, sharpening up the halo profile, and reducing junction leakage. PMOS it was not quite so positive, since the halo profile was sharpest with the Ge + F combination; but overall the clusters seemed to do best. Boron clusters were also tried in pMOS, but that led to an increase in V_t variation.

37.4
Toshiba did an interesting analysis by atom probe of platinum doping in nickel silicide. This is an ongoing trend that we have seen in our analyses, almost the majority of 65nm parts have Pt-doped silicides (Intel is an exception); it is claimed to reduce contact resistance. Atom probe is a relatively new technique, but it has much better resolution than SIMS, since it counts individual atoms (check www.Imago.com).

The analyses showed that the platinum segregated both at the surface and the silicide interface in the source/drains, which actually jives with an atom probe analysis [3] we did of a UMC-fabbed Xilinx part; we saw the same feature in the gate polysilicon. And it did help contact resistance.

Phew! That's it for IEDM '08. Maybe I'll see you next year... If the industry's still around. -- D.J.

[3]  L. Klibanov et al, “Doping Profile Measurements in a 65-nm Commercial Product Using Atom Probe Tomography”, Proc. ISTFA 2008, pp. 297 -300.

How Big Does It Really Need to Be?

Contributed by Kevin Gibb

After tearing down some of the latest gaming cards to get at the advanced node devices inside, I was reminded of a song by Joe Walsh where he waxes on about how his Maserati did 185 mph. The suggestion is that there is no point in having such a car because he lost his license anyway, and you don’t need (or are not allowed) to do 185 mph. But in the world of sports cars, what you see is not always what you need. The same holds true in high-end gaming cards.

A case in point is a gaming motherboard that came into our labs a few months ago. It looks pretty. Pink and green expansion board slots, pink, yellow, and purple connector sockets, and perhaps the biggest heat pipe that I have seen inside a desktop computer. It just screams POWER and PERFORMANCE, or does it?

A quick look at the Intel website seems to indicate that the NH82801IR I/O controller consumes 4.5 watts and the NU82X48 consumes 27 W. By comparison, the Core^TM2 Extreme Desktop Processor comes in at 136 W. So, I question whether the Silent-Pipe is a bit oversized for the job.

Figure 1 – Motherboard with Silent-Pipe

I have been collecting heat pipes from computers over the last few years and show three below in Figure 2. The Silent-Pipe is shown in the middle, dominating both the heat pipe extracted from an Intel Prescott computer (~100 W dissipation) and the laptop’s heat pipe, which we estimate to be dissipating about 15 W.

Now the Prescott and laptop heat pipes both use fans to help remove heat from the processors. So, one must wonder why the makers of the Silent-Pipe went with a passive air exchange, without the assistance of a small fan. Today’s games typically have the volume turned up to 11, so a fan can’t make that much of an impact on the gaming experience, can it?

Figure 2 – A Comparison of Heat Pipes

Heat pipes are fairly simple devices. They have a pipe partially filled with a liquid, an evaporator plate, and a condenser plate. The evaporator plate is heated up to the boiling point of the liquid, which then diffuses down the pipe to the condenser, where it gives up its heat, turning back into a liquid. Capillary action then draws the liquid back to the evaporator.

The type of liquid, and the vapor pressure inside the pipe, sets the temperature at which the heat pipe operates. The easiest way to find the temperature is to put the thing on a hot plate and cook it (Figure 3). The hot plate is simmering away at 325^oC, while the top of the evaporator is at a still fairly warm 50^oC. This is close to the boiling point of both methanol (65^oC) and acetone (56^oC) at atmospheric pressure. Pulling a small vacuum in the pipe would reduce the boiling point, so either acetone or methanol could be the heat transfer fluid.

The 50^oC sets the upper case temperature for the NU82X48 memory controller hub (MCH), and is well below Intel’s 92^oC maximum for the MCH case [1].

The condenser is hanging off the front of the hot plate. This is where the excess heat is being dumped.

Figure 3 – Cooking the Heat Pipe

The heat flow from the evaporator to the condenser relies on the large latent heat of fusion of the liquid. The heat transfer (in boiling or condensing) is far higher than the thermal conductivity of any metal (even diamond). So large amounts of heat can be moved quite easily by the evaporated liquid (vapor). The heat transfer will often be limited by the cooling plates on the condenser and the air flow across its fins. In this case, both the evaporator and condenser are finned to get rid of the heat. But why not add a small fan? Blowing a bit of air across the condenser will greatly increase its cooling ability and does not add much cost. Or perhaps we have forgotten that the microprocessors in our computers are already fan cooled (much like the engines in our cars).

Now diffusion drives the hot gas from the evaporator to the condenser, which solves half of the heat transfer problem. But it has been a bit of a puzzle as how to get the condensed liquid back to the evaporator. One way would be to use gravity as the return mechanism, but this does not seem to be a good design for laptops and desktops, which might be placed in any odd direction. It turns out that capillary action does the trick, with three designs being offered; grooved tubes, wire meshes, and sintered powders.

Peeling open a copper pipe from a laptop heat pipe reveals a series of ridges that appear to have been made using a fairly low cost extrusion process. This same ridged structure is used by the Silent-Pipe.

Figure 4 – Grooves Inside of Laptop Heat Pipe

The capillary action used to draw the liquid back to the evaporator works better if there is a large surface area to wet the liquid. We show the heat pipe used for an Intel Prescott microprocessor in Figure 5 (the Prescott dissipates about 100 W, three times that of the memory controller hub in Figure 1). It has a sponge-like layer (sintered copper) on its inside surface. This material has a much higher surface area than the grooved pipe above, and we would think, a significantly higher heat transfer rate.

Figure 5 – Sintered Copper Capillary

The heat pipe assembly used for the Prescott microprocessor is shown in Figure 6. It is about half the mass of the Silent-Pipe, but transfers more than three times the heat. We also note that the fins are steel, not copper, which cuts its manufacturing cost.

Figure 6 – Intel Prescott Heat Pipe Assembly

So has form overridden function? And is the Silent-Pipe for show? Well, I am too busy to speculate much further. I have just loaded up “Test Drive Unlimited” on my PC. I think I’ll try the Maserati.

References

[1] http://www.intel.com/Assets/PDF/designguide/317612.pdf

It’s less than a month now to the process geek’s techfest, the International Electron Devices Meeting on December 15-17 in San Francisco.  IEDM is the prime conference for semiconductor devices, and the place where the chip companies like to strut their technology.  It alternates between San Francisco and Washington – this year is San Francisco’s turn. 

Our purpose in attending the conference is to see what technology is likely to come on stream in the next year or so.  As usual there’s the usual wide range of stuff, but we’ll likely be sitting in on the 32-nm face-off between IBM, TSMC, and Intel, as well as the other advanced CMOS papers.  The IBM/AMD/Freescale alliance is claiming the smallest SRAM cell ever at 0.1 µm², and Qimonda has the smallest DRAM cell (0.013 µm²) using a 6F² architecture similar to the new buried wordline stacked-cell technology that they have just started shipping.

0.1 µm² SRAM cell from IBM/AMD/Freescale alliance (Source IEDM)

There are also some low-k dielectric papers from NEC that could soon be relevant (we think we’ve just got our first 2^nd-generation low-k part – we’ll know in a couple of weeks), and there are some interesting 3-D papers.  And of course there are a few blue-sky research papers that could be the clues to the disruptive technologies that we’ll see five to ten years out.  The advanced program is down-loadable on the IEDM site here.

In addition, the last two years we’ve hosted show-and-tell sessions, and we plan on doing another one this year, on the Tuesday (16 December), after the afternoon’s papers are finished and before the evening panel discussions.  The topic will be “A Pot Pourri of Innovation in 2008”, and I’ll be going through some of the advanced devices that we’ve seen in the last year.  Last year we focused on transistor structures, but this year we’ll spread the net broader, and cover everything from image sensors through flash and advanced logic to TSVs. 

Consider this as an invitation – you can get registered on our website.  I hope to see you there!

High-k Gate Dielectrics – the Future Is Friendly for NAND Flash

Contributed by Kevin Gibb and Haowen Gu

In hindsight, 2005 came in with a bang, as 90 nm CMOS, DRAM, and flash memories hit the market. Intel introduced strain engineering to boost their transistors, and for awhile it seemed like CMOS was heading into overdrive.

Intel brought us strain engineering, SiGe epitaxy, and last fall, metal gates. It was easy to ignore DRAM and flash, especially since the businesses are fighting a prolonged pricing slump and what seems to be significant overcapacity. Despite this, Toshiba kept on shrinking its NAND flash, offering more memory at ever cheaper prices.

We begin our journey at 90 nm (circa 2005). Toshiba’s 90 nm process came into our labs in 2005, packed into Apple’s then newly released iPod Shuffle. The Shuffle, like the iPod Nano, came with flash memory as opposed to hard drives. At one point, demand for flash memory by two iPods became a major driver for Toshiba and Samsung’s flash businesses.

Toshiba’s 90 nm flash cell is shown in Figure 1. And as with earlier generations, it employs a tungsten silicided wordline, ONO interpoly dielectric, oxide tunnel dielectric, and fairly conventional oxide and silicon nitride sidewall spacers.

Figure 1  Toshiba 90 nm Flash

The shrink from 90 nm to 70 nm brought in some modest design changes to the dielectrics, filling the gaps between adjacent cells. Tightening up the cell pitch results in an increased intra-line capacitance, and thus, increased cross-talk between cells. While this is a problem for single level cells (SLC), it seems fatal for multi-level cells, where the stored charge on the floating gates yields fairly small increments in the four threshold voltages needed to store two bits of information. The solution, as shown in Figure 2, was to remove the silicon nitride sidewall spacers from the flash array and just use oxide. This reduces the intra-line capacitance, reducing the cell to cell cross-talk.

The top of the array is still sealed by a silicon nitride contact etch stop layer.

Figure 2  Toshiba 70 nm Flash

The use of four poly layers in the flash array was initially a bit of a puzzle. Why four when three could do? It is fairly clear from Figure 3 that the poly 3 layer is being used as an etch mask for the interpoly via that electrically joins all four poly layers together. This is needed by the bitline and sourceline select transistors at the ends of the NAND flash array (every 32 wordlines), as well as for the peripheral transistors.

The poly 1 is about 30 nm thick, about the right thickness to work as an implant mask for the underlying N-doped channel region. We speculate that this layer allows Toshiba to tune the implant profile, and perhaps reduce the off-state leakage currents of the cell transistors.

Figure 3  Interpoly Via

By 2007, Toshiba had partnered with SanDisk to produce a 56 nm node, 64 Gbit flash. The cell (Figure 4) shows a return to the three poly layer gate structure, which now has a cobalt silicided wordline. The switch to cobalt from silicide yields a lower wordline resistance, which should reduce the read times for the cells (t=RC).

Figure 4  SanDisk/Toshiba 56 nm NAND Flash

The interpoly dielectric, which for the longest time had been a three-layer structure of oxide, silicon nitride, and oxide (ONO); now features two new, very thin layers of silicon nitride. The one layer, lining the sides of the poly 1 gate, is just visible in Figure 4. The five layers are more clearly seen in Figure 5.

Toshiba is not alone with this five layer dielectric, as Powerchip Semiconductor has just published a paper showing the same [1]. The thin silicon nitride layers appear to have been formed by plasma nitridation of the polysilicon floating gate (after STI etch back) and the top oxide layer, respectively. Nitriding the poly 1 seems to improve the surface quality, by smoothing the polysilicon and reducing surface states (good thing when the stored charge can be lost through surface recombination states).

However, this does not explain the need for the top nitride layer. Powerchip goes on to suggest that the two thin nitride layers help prevent formation of oxide bird’s beaks within the interpoly dielectric during later thermal processing. The uniform separation of the poly 2 and poly 1 gates, seen in Figures 2 and 4, seem to bear this out.

Figure 5  Interpoly Dielectric

At about the same time as the 56 nm flash product was making its way onto the market, Toshiba presented its 43 nm MLC flash at the Fall 2007 IEDM conference [2]. Their cell can be seen below in Figure 6. The process seems evolutionary as opposed to revolutionary, as much of the processing remains unchanged from their 70 nm node (i.e. Cu bitlines and CoSi₂ wordlines).

Cobalt silicide is again used to lower the wordline RC time delays. The top of the silicide is rounded, much like the silicide in their 70 nm process. Toshiba suggests that this is a deliberate design feature to reduce the electric fields, and hence, reduce tunneling currents.

While the interpoly dielectric looks the same as Toshiba’s 56 nm process; it is not. The thick silicon nitride middle layer has been replaced by a metal oxide, which almost certainly increases the capacitive coupling between the wordline and floating gates, as well as reducing gate leakage currents.

The adoption of metal oxide as a dielectric is not new, as it reminds us of Samsung’s AlO/HfO DRAM capacitor dielectrics of a few years back.

Figure 6  SanDisk/Toshiba 43 nm NAND Flash

The tunnel oxide underneath the poly 1 has not changed very much over the last few generations of flash memories, staying in the range of 8 to 9 nm thick. This is needed to prevent the leakage of the floating gate’s stored charge. But as the gate length and width shrink, so too does the charge stored on the floating gate. This we estimate to be about 100 electrons for the 43 nm node, which is not much when the cell is being asked to remember its state for up to 10 years.

Simple scaling of the cell as 1/L² will result in too few electrons being stored. The solution is likely to be increased capacitive coupling of the interpoly dielectric, so as to apply greater programming voltages onto the floating gate, and hence, more stored charge. So the future looks friendly for high-k gate dielectrics.

We must also anticipate the replacement of the tunnel oxide by high-k dielectrics.

References:

[1]  C. Yuan et al, “Improvement of Interpoly Dielectric Characteristics by Plasma Nitrideation and Oxidation for Future Flash Memory,” IEEE Electron Device Letters, Vol. 29, November 11, 2008, 1199-1202

[2]  M. Naguchi et al, “A High Performance Multi-Level NAND Flash Memory with 43 nm-Node Floating Gate,” IEDM, 2007

eDRAM – The Future is Up, Not Down

contributed by Kevin Gibb

Embedded DRAM, or eDRAM as it is called now, seemed to be a hot idea back in 2003, when Sony introduced their 90 nm node EmotionEngine^TM with their PSX Playstation. A big argument for its use is the speed advantage of having DRAM right beside your logic blocks.

At that time the commodity DRAM makers were split into two design camps: those with deep trench capacitors, and those with stacked capacitors.

Sony’s 90 nm node embedded DRAM trench capacitor is shown below in Figure 1, and it follows IBM’s bottle-shaped design. In this case, the device appears to have been fabbed by Toshiba for Sony. 

Figure 1  Sony/Toshiba 90 nm Embedded DRAM (2004)

At the time, it was not clear to us how far the trench eDRAM technology could be scaled. But the likes of IBM hinted that it had legs. And indeed, Qimonda is offering deep trench capacitors for their 70 nm DRAM product, as shown in Figure 2, and they claim to be putting a 58 nm version into production.

The future for trench DRAM seems dim, as most manufacturers are abandoning trenches in favor of stacks. My last check of the business indicated that Nanya and Qimonda were the lone trench manufacturers, with Hynix, Micron, Powerchip, and Samsung all using stacked capacitors.  Add to this, the announcement that Qimonda is switching to stacked capacitors, and the future seems to point up, not down.

Figure 2  Qimonda 70 nm DRAM (2008)

So, we have been looking for stacked embedded DRAM in a variety of ASICs for some time now. Word is out that Nvidia has been using TSMC’s 65 nm eDRAM for their handheld GPU’s as early as 2007. However, we’ve not had much luck in finding them so far.

Our searches have uncovered some 90 nm eDRAM by NEC and TSMC. NEC’s process showed up in 2005, while TSMC’s 90 nm eDRAM arrived in our labs this summer inside an XBOX 360.

The NEC eDRAM is shown below in Figure 3. The storage capacitor is placed above the tungsten bitlines (just visible in the left figure). A tungsten metal plate connects the inner capacitor plates to a common bias voltage, while the TiN outer plates are connected to the access transistors. A thin layer of the high-k dielectric ZrO forms the capacitor dielectric.

The process seems complicated as nine levels of dielectrics are needed to support the capacitors and metal 1. And metal 1 forms the local interconnects for the peripheral transistors, requiring three sets of tungsten plugs to go from metal 1 down to the transistors. Two of these plugs can be seen below the capacitors in Figure 3.

The TEM image of the capacitor (right image in Figure 3) gives some clues to its manufacture, which follows a damascene process. Like the Cu damascene process, a trench is opened in the pre-metal dielectric, which supports the TiN outer plate. The TiN only goes part way up the sides of the capacitor, suggesting a sacrificial fill and chemical-mechanical planarization step. Removing the fill material, lining the capacitor with a high-k ZrO dielectric, and depositing the TiN outer plate and W common bias plate completes the capacitor. Wow! That is a bit of work.

Figure 3  NEC eDRAM Memory and Capacitor

TSMC, on the other hand, has placed its capacitor beneath the metal 1 bitlines, as shown in Figure 4. This process gets rid of one of the W plugs, so at least one less lithographic step, and one less metal being used for the capacitor plates.

The trench etch also seems to be a bit better, as it is completely flat across the bottom, stopping at the top of the contact, whereas, NEC’s etch has left the W plug standing a bit proud.

So with at least two less masks, and tidier processing, it appears that TSMC has the lower cost process.

Figure 4  TSMC eDRAM Capacitor

But the eDRAM business has moved on, with TSMC, IBM, and UMC all advertising 65 nm eDRAM, and seemingly, IBM talking up eDRAM as being their number one priority for the 45 nm node [1]. The eDRAM may turn out to be a key competitive advantage for the foundries.

So we are on the hunt for TSMC’s 65 nm eDRAM to see what the future holds.

[1]  http://www.semiconductor.net/blog/270000427/post/520029052.html

Inside the Qualcomm mirasol IMOD MEMS Display

contributed by Rajesh Krishnamurthy

The Qualcomm bichrome 1.1” mirasol^™ interferometric modulation (IMOD) display device is intended for use as a display in Bluetooth headsets, indicators, MP3 players, industrial applications, and as a secondary display in cell phones. The key benefits of this display over comparable reflective LCD displays are features of low power, high contrast (8:1 ratio between active and dark) and high reflectivity (60%), which enables the user to read across a wide range of ambient lighting and environmental conditions. Further, the datasheet information indicates that the IMOD display has a factor of 1000 higher switching speed (10 µsec) compared to similar LCD displays. Additionally, the IMOD displays, when compared to similar OLED displays, require 10 times less power (10s of microwatts), have a longer life span, better readability in bright lights, and are less expensive as they can be manufactured on a typical flat panel display facility.

According to YOLE Développement, the world leader in the analysis of the MEMS market, the MEMS-based displays market is estimated to be US$1.1 billion in 2008. By 2012, it is forecasted to reach US$2.8 billion. This represents a compound annual growth rate (CAGR) of 26%, mostly because of the growth of new applications such as companion projectors. MEMS-based displays are of two kinds: direct view (such as mirasol™ from Qualcomm) or projection view (such as DLP^® from Texas Instruments). The IMOD-based display developed by Qualcomm is a direct view micro display.

Qualcomm started the development of this device by acquiring Iridigm, a privately held company, in 2004 and its patented IMOD technology based on micro electro mechanical systems (MEMS) structure, combined with thin film optics. Since then, Qualcomm has been gradually making the technology high-volume production worthy, and branding its mirasol™ display products. For example, Qualcomm has released mirasol™ displays for different products, including, a 1.1” display for the Bluetooth mini-bridge stereo headset ARWH1 from Acoustic Research, a 1.2” display for the Hisense Hs-c108 cell phone, and a 1.1” display for a wireless and mobile monitoring 3G phone, released at the KTF SHOW¹. The monochrome mirasol™ displays are manufactured primarily for Qualcomm by Prime View International in Taiwan². Further, Qualcomm has recently demonstrated the first 0.9” IMOD color mirasol™ display at the SID 2008 conference³.

The mirasol™ IMOD features an integrated superstructure, fabricated with two glass plates glued together, with the top glass plate used for the MEMS pixel array and the bottom glass plate used for capping the MEMS structures. Figures 1 and 2 below show the front and back images of the display device. The bottom glass plate only partially covers the top glass plate where the MEMS structures are located, and has a cavity located such that it resides below the MEMS structures in the superstructure. The superstructure also features a silicon ASIC die bonded to the underside of an exposed area of the top glass plate and connected to the pixel array.

Figure 1  IMOD Front

Figure 2  IMOD Back

The mirasol™ MEMS device die markings in Figure 3 confirm the origins of the device.

Figure 3  Mirasol™ IMOD MEMS Device Die Markings

The IMOD module is very similar in size and configuration to an OLED display module that we found in a Freestyle Audio MP3 player. It is interesting to note that Freestyle Audio is set to incorporate the color mirasol™ displays into its products in the near future³. This indicates that the IMOD display module has been designed to work as a simple replacement for either LCD or OLED modules in downstream products. Further, it is a design win over OLED products for the rugged MP3 players, and may be a sign of things to come for other products that require small size display, longer operation without battery recharging, and work in rugged outdoor conditions. Qualcomm has announced a collaboration with Foxlink (Cheng Uei Precision Industry Co. Ltd.) to combine expertise, and open a new dedicated mirasol™ fabrication plant in Taoyuan, Taiwan, due to be fully operational in 2009, to manufacture its color display products⁴.

Figure 4  OLED Front

The die markings on the ASIC die shown in Figure 5, attached to the underside of the display module, show that it is supplied by Dialog Semiconductor. Dialog was chosen by Qualcomm to be the supplier for this driver back in 2005⁵. It is interesting to note that Qualcomm chose to include the Qualcomm MEMS Technologies logo, the butterfly, on the ASIC die and not on the MEMS die.

Figure 5  IMOD ASIC Die – Die Marking 1

Figure 6  IMOD ASIC Die – IMOD Butterfly Die Marking 2

Structural Details of the Qualcomm mirasol Device

The MEMS pixel is an optical interference type reflective pixel, which consists of a movable bilayer metal plate situated below a stationary metal plate, as illustrated in Figure 7, a schematic image disclosed by Qualcomm⁶.

Figure 7  Schematic Diagram of Mirasol™ IMOD MEMS Device 

The pixel array consists of rows of partially transparent/reflective stationary metal plates, as seen in Figure 8, and columns of movable reflective bilayer metal plates placed vertically with respect to the stationary metal plate direction. The incident ambient light reflects from the bottom bilayer plate, and can constructively interfere with the incident light of a certain wavelength. With no applied voltage between the plates, the device is in a mechanically relaxed state, and an observer sees a sharply illuminated cell due to this constructive interference. This is termed as an “ON” state. However, when a potential difference is applied between the plates, an electric field with attractive force is formed between the top stationary electrode connected to the column circuitry and the bottom movable bilayer metal plate connected to the row circuitry. The corresponding pixel is charged, and if the potential difference is high enough, the bilayer metal plate deforms, collapsing the height of the air-filled cavity. This results in a destructive interference of the visible light, and the pixel is now considered to be turned “OFF.” The bilayer metal plate position can be shifted back up to the “ON” state position only by further applying a sufficient potential difference. This method of operation of the pixels, by turning on at the intersection of activated column and row elements, is analogous to LCD and other display technologies. However, this MEMS interferometric device can be operated at much lower power than the LCD or other conventional displays, due to this observed hysteresis in the up and down shifting of the bilayer plate.

We opened one of these MEMS display modules. Below are some optical, SEM, and TEM images that reveal some of the general structures of this device.

Figure 8 and Figure 9 show optical plan-view and SEM tilt-view images of the movable metal plates. Rows of movable plates are supported by various support posts. The movable metal plate is separated from the stationary plate by a cavity, which is created by etching the sacrificial layer that supported the movable metal plate, through the etch release holes.

Figure 8  Plan-View Image of Movable Metal Plate

Figure 9  Tilt-View Image of Movable Metal Plate

The movable and stationary metal plates, the cavity, and the support posts are seen in the SEM cross section of Figure 10, and TEM cross section of Figure 11. The movable bilayer metal stack is made up of two metal layers. The thicker metal layer of this bilayer is the mechanical support layer and the thinner layer is the reflective layer. The thickness and the type of the mechanical layer are chosen to provide a certain residual tensile stress. This tensile stress provides the mechanical force to pull the movable layer away from the optical stack when the modulator is unactuated or relaxed. A second layer of metal, above the stationary metal blocks, light in inactive areas like support posts and dark pixels.

Figure 10 – IMOD SEM Cross Section Structure of Active Pixel

Figure 11 – IMOD Structure in Detail – TEM

References

1.  http://www.qualcomm.com/products_services/consumer_electronics/portable_devices/index.html

2.  http://www.qualcomm.com/news/releases/2005/050329_QMT_print.html

3.  http://www.qualcomm.com/news/releases/2008/080519_Qualcomm_Pioneers_Industry_First_IMOD_Color_Display.html

4.  http://www.qualcomm.com/news/releases/2008/080505_Qualcomm_and_Foxlink_Combine_Expertise.html

5.  http://irpages.equitystory.com/cgi-bin/dialog_semiconductor/show.ssp?fn=showNewsStory&language=English&newsID=22691

6.  http://www.qualcomm.com/common/documents/brochures/MCL1039_Bichrome_1.1a_new.pdf

Not Your Brownie Camera Anymore

contributed by Kevin Gibb

Cell phone cameras just keep getting smaller and better. We've been taking them apart for a number of years now and have watched the evolution and technology on the CMOS image sensors. The relentless march to smaller technology nodes has allowed the image sensor designers to employ smaller pixels, leading to smaller dies.

A recent packaging trend that we've seen is the addition of an ASIC to the camera module. These ASICs often provide control signals for the image sensor, processing of the captured images, and in some cases shutter and focus control of the optical module. Samsung and Sharp have both added camera control ASICs to their modules, which are shown in Figure 1.

Sharp has stacked their image sensor die overtop the ASIC, then popped the optical module over the two dies.

 Figure 1 – Samsung and Sharp Camera Modules

My interest is the Samsung module, which has an MTekvision MV93173 camera DSP mounted on its backside (Figure 2). This DSP features auto focus, optical zoom, mechanical shutter, digital stabilization, and hot/dead pixel correction in addition to its regular image processing. The prospect of zoom and focus in an 8.5 mm x 8.5 mm x 6.5 mm large module grabbed my attention.

The side-view package X-ray tells part of the story, as one can readily see three sets of lenses overtop the CMOS imager die. The MV93173 control ASIC is bumped to the backside of the printed wiring board that supports the CIS die. This ASIC is wire bonded to its package. What is not seen in this X-ray are the solenoids used to drive the lens elements and their supporting springs.

 Figure 2 – Back Side and Side Package X-Ray, Samsung CIS Module

Stripping away the outer metal packaging turned up some small permanent magnets placed along the outer edges of the package, strongly hinting of the use of solenoids to control some lenses. These coils are revealed in the lens assembly X-ray, shown in Figure 3. Three sets of lenses are clearly visible, as are two sets of coils. Both the top and bottom lenses are suspended by fine wire springs. This might suggest that both focus and zoom are available, but unfortunately, the camera specifications only indicate auto focus.

The camera supposedly has 4x digital zoom, but it is a bit of a shame that they chose not to use an optical zoom, since their lens design does allow for some pretty sophisticated lens control.

Figure 3 – Lens Side-View X-Ray

The optical performance for this camera is likely to be pretty good. Here one can estimate the performance by calculating the modulation transfer function (MTF) of the image sensor (red curve in Figure 4) and the optical transfer function (OTF) of the aperture supporting the outermost lens (blue curve). The aperture supporting the lens should have a better OTF than the lens, as the lens will have imperfections that degrade its performance.

One wants high values (near 1) for as high a spatial frequency as possible, and the lens design, rather the aperture, seems to deliver; as the aperture OTF lies above the image sensor (MTF) at the higher spatial frequencies.

Figure 4 – Lens OTF and Image Sensor MTF Functions

So a miss on the optical zoom, but the auto focus is a step up from earlier fixed focus cell phone cameras. And so again, we say goodbye to the Brownie camera with its pinhole lens.

Ultra thin yet still reliable

An examination of advanced node liners

contributed by Kevin Gibb

While we tend to think of the transistor, its contacted gate pitch, and SRAM cell size as being the big story, manufacturers have been making small changes to their copper metal barriers. The roadmap has been calling for the thinning of the copper liners (solid line Figure 1. But until recently, the chip makers seemed to be following their own paths, that is, until the 45 nm node arrived. Now we are seeing some significant changes.

Figure 1 – Metal 1 Sidewall Liner Thicknesses

Intel was first to market at 45 nm, followed shortly after by Matsushita. Both have done some work with their metallization. Figure 2 shows the bottom portion of Intel’s metal 1 line. The metal 1 line lies within a low-k carbon doped oxide, which reduces the interline capacitance. Its low density also causes the trench etch to proceed at slightly non-uniform rates, resulting in the roughen bottom seen in Figure 2. The sidewalls, in contrast, are pretty smooth.

The Ta-based liner appears to have been deposited in two steps, with a more amorphous layer on the outside and granular layer on the inside. This two-layer structure is pretty common, and we think that it has to do with a change in the nitrogen content within the Ta metal.

At 4 nm thick, the sidewall liners are among the thinnest we have seen to date, and are a bit ahead of the ITRS roadmap (Figure 2).

Figure 2 – Intel 45 nm Metal 1 Liner

Matsushita has been showing game for its 65 nm and 45 nm processes. They don’t seem to be trying for the high performance market, with the likes of Intel, TSMC, and UMC; they have likely carved out a niche for low cost dies.

Their process features a 130-140 nm metal 1 pitch (Figure 3), which is the smallest that we have seen to date in a logic process. 

Figure 3 – Matsushita 45 nm Minimum Pitch Metal 1

The metal 1 lines are formed in an undoped oxide, giving their metal lines very smooth edges. This likely lets them use the extraordinarily thin, 3 nm thick liners seen in Figure 4. We also note that these liners feature a fine grained structure throughout the thickness, in contrast to the two-layered liner used by Intel.

Figure 4 – Matsushita 45 nm Metal 1 Liner

Chemically analyzing these thin Ta-based liners has proved to be a challenge, as our TEM-EDS (energy dispersive X-ray spectroscopy) shows somewhat poor sensitivity to the nitrogen in the TaN layers. TEM-EELS (electron energy loss spectroscopy) does a somewhat better job, and we occasionally take a closer look at the liners, as was the case for a UMC fabbed 65 nm device shown in Figure 5.

The two-layered structure is clearly resolved in this figure, as well as on isolated metal 1 lines. So we did a TEM-EELS line scan through the liner of an isolated metal 1 to take a closer look, with the results being plotted in Figure 6.

Figure 5 – UMC 65 nm Node Metal 1

The bottom of the scan started in an underlying oxide (PMD 4), then entered the bottom most portion of the liner. N is readily detected, indicating that the outer portion of the liner is indeed TaN. The N line shows a drop near the top of the liner, as it approaches the copper fill. Therefore, we can definitely say that the inner portion has a lower N content, and perhaps it is Ta alone.

Figure 6 – TEM-EELS Line Scan Through Bottom of Metal 1 Liner

The ITRS roadmap calls for further thinning of the liners, to as thin as 2 nm around 2015. Though how this will be done is uncertain. As part of our reverse engineering business, we shall continue to tear apart the latest chips to find the answer being used by the industry.

MEMSIC Goes its Own Way

Contributed by: Kevin Gibb and St.J. Dixon-Warren

Many of us think of accelerometers as being made of swinging masses on springs. But this is not the only way of doing things, as MEMSIC has nicely demonstrated with their thermally based technology. They claim it to be disruptive; principally due to low cost.

The timing of the completion of our analysis is interesting because it follows on the heels of a fairly high profile event for the manufacturer. The spotlight seemed to be on MEMSIC over the last month where, at the Olympic opening ceremony, there was more hot about the torches than just the fire. Spectators were seen waving 92,000 red, green, blue, yellow and white dots at the opening ceremonies that incorporated  MEMSIC's thermal-based MEMS technology.

Unlike conventional accelerometers that use little bits of polysilicon or silicon for their proof masses, MEMSIC uses the movement of a “bubble” of a hot, heavy gas under the influence of acceleration (part of the ‘secret sauce” of their design is its composition). It is worth noting that MEMSIC has chosen a gas with higher heat capacity and a lower thermal conductivity than air.

The MEMS portion of their sensor is shown in Figure 1. It has a central heater ring supported on a dielectric bridge. This heater is used to heat the proof mass, in this case the high molecular weight gas. The sensor is made from a thermopile (formed using a series of 40 thermocouple junctions on each side) that surround the heater. The hot junctions lie on a dielectric bridge surrounding the heater, while the cold junctions are at the periphery of the cavity, buried under metal.

The heated gas forms a small bubble overtop the heater and exhibits a temperature gradient, being hottest in the center, and coolest at the periphery.  MEMSIC applies its cleverness, in that the bubble of hot gas will naturally lag the motion of the die, under acceleration.  This results in the bubble being displaced away from the center, with the one side of thermopile pair sensing a bit hotter than the other. A differential signal is detected and translated into a digital measure of the acceleration by the surrounding ASIC circuitry.

Figure 1. Heater Ring and Thermopile Sensors

The heater ring show in Figure 2 is supported by a dielectric bridge that has been patterned and etched. This etch has removed a portion of the silicon substrate to form a cavity underneath the heater and thermopiles. The polysilicon heaters seen in this image followed a meandered path over the dielectric bridge.

MEMIS has described their process as being a CMOS-MEMS process. And it appears that TSMC does the CMOS processing for them, with MEMSIC doing the MEMS release etch and packaging themselves, likely at their facility in China. MEMSIC also maintains R&D facilities in the United States.

Figure 2. Heater Ring

The thermocouples, a stalwart of temperature measurements dating back many decades, are formed as series Al/polysilicon junctions, as shown in Figure 3.  These lie nearest the central heater and form the hot junctions. As mentioned earlier, the cold junctions are buried under metal 2, along the edges of the cavity. Suitable doping of the polysilicon will likely give good Seebeck coefficients for the junctions, while tuning the metal and poly linewidths to optimize their electrical resistance and thermal conductance has likely achieved a high sensitivity (signal to noise ratio).

Figure 3. Hot Thermocouples

These are innovative devices that deliver impressive specifications at a low cost, and MEMSIC is targeting its marketing across the full range of applications. This particular device has a 50,000 g shock survival rating and was found in a consumer product - unless the product was a hammer (it wasn't), this combination is not entirely intuitive. Tracking MEMSIC's success in both industrial and consumer markets to see what feature combinations are winning what sockets will be interesting.

Contributed by Kevin Gibb

The DMOS transistor, while fairly common in high voltage mixed signal IC’s, is not often encountered by many CMOS IC designers. We are seeing an increased interest in IC’s for automobile control electronics, inkjet printheads, and power supplies. So we think a look at some devices that have passed through our labs might be of general interest.

DMOS transistors have been used in automobiles for more than a decade now, where their ability to sustain high drain voltages and large drive currents has proven quite useful. These attributes have not been lost on chip designers as DMOS transistors are finding new uses in inkjet printhead drivers and high voltage switched power supplies, among others.

Inkjet printheads work by ejecting small bubbles of ink through nozzles onto a print media such as paper. A metal film resistor (firing resistor in Figure 1) is typically used to heat the ink creating small vapor bubbles along its surface. This process is quite rapid, with the sudden formation of the bubble driving the remaining ink in the ink cavity then through the nozzle onto the print media.

Figure 1 Firing Resistor and Nozzle from a Kodak Printhead

This process requires lots of power, which is why these resistors are almost always driven by large DMOS transistors. Figure 2, for example, shows a pair of lateral double diffused MOS (or LDMOS) transistors used by a Hewlett Packard printhead.  The source contact is shared by two transistors, having their polysilicon gates located between the common source N⁺ contact diffusion and the two drain contacts.  A P-body diffusion lies beneath the source contact and extends about 0.6 µm laterally underneath the gates, to define the effective gate length for the transistor. This gate length is considerably shorter than the 2.5 µm long polysilicon gate. For a number of years, this ability to create a transistor with an effective gate length, shorter than the physical gate length, was an attractive feature for DMOS transistors.

The transistor, when switched off, will have quite large electric fields at the drain end of the polysilicon gate. Lifting the gate poly up over a small segment of field oxide isolation (FOX) reduces the electric field at the drain end of the gate, protecting the gate oxide from avalanche breakdown.

Figure 2 HP Printhead DMOS Transistor

Figure 3 is a scanning capacitance image taken of the transistor, which shows the N-diffusions in yellow and the P-diffusions in blue. A 3 µm deep N-well surrounds the transistor and forms the N-drift region, that connects drain contact to the transistor.  This N-well is lightly doped (about 8x10¹⁵ cm^-3) so as to support large drain bias voltages without breakdown. In this case, the N-well doping suggests a breakdown voltage of the order of 50 V.

The lightly doped N-drift regions, while giving high breakdown voltages, come at the expense of high series resistances. So very wide transistors are needed to achieve high drain currents.

Figure 3 SCM Image HP DMOS Transistors

Figure 4 shows a variation to the DMOS transistor in which the P-body is electrically connected to the source contact by a P⁺ implant. This design is used in HP’s HP8250 printhead, which predates the transistor shown in Figures 2 and 3.  Tying the P-body to the source comes from conventional CMOS transistors, whereby the P-well or P-tub is tied to V_SS (and similarly the N-tub to V_DD). Asserting a ground bias to the P-body keeps the transistor threshold voltage fixed and assures low leakage currents for the off-state transistor.

Figure 4 HP DMOS Transistor

One might be tempted to think that this was pretty much it for DMOS transistor design, but the folks at Power Integrations have some novel designs to add to the mix. They are in the business of making high voltage power conversion IC’s, and by high voltage their DMOS transistors can sustain an impressive 700 V before breakdown. These transistors are made on the same die as their BiCMOS control circuitry.

The N-drift regions have a graded doping profile that gives their high breakdown voltage, but at the expense of a high resistivity drain region (or high on-state resistance). Power Integrations’ overcomes this by adding a P-buried layer, which they describe as creating JFET conduction channels within the N-drift region.  This P-buried layer appears to accomplish two tasks, first it partially depletes the surface portion of the N-drift region yielding a higher breakdown voltage, and second, it allows for a nearly doubling of the charge in the JFET channels, lowering the on-state resistance of the transistor. The details of this are disclosed in their patent US 6,207,994.

Figure 5 Power Integrations High Voltage DMOS Transistor

But this is not the only way to make high voltage transistors, as Infineon has used deep P-diffusions to achieve high breakdown voltages (see Figure 6).  The transistors are formed in an N-epi layer having an approximately 2x10¹⁵ cm^-3 doping. Under large off-state bias conditions (the chip has a bias rating of 800 V), the N-epi is believed to be fully depleted, protecting the drain edge of the transistor gate from the high voltages.

When turned on, the channel conducts current from the source contact, through to the N-epi drain, and out through the bottom of the die.

The P-body exhibits a lobed profile indicating that the devices were fabricated as a series of N-epi growths and P-implants. Not a cheap process, but likely quite effective for making these high voltage transistors.

Figure 6 Infineon SPP02N80C3 Cool MOSTM Power Transistor

Figure 7 is a higher magnification view of the polysilicon gate, the P-type channel diffusion, and the source contact. Like the second HP DMOS transistor (Figure 4), Infineon has used both P⁺ and N⁺ source implants. The P-diffusion defines a 2 µm effective gate length for this transistor.

Figure 7 SCM Gate, Channel and Source Contact

It’s easy to become engrossed in the semiconductor industry’s relentless march to smaller geometries (45 nm node as of fall 2007) and reduced bias voltages (~ 0.8-1 V V_DD), that we sometimes forget about the other end, high voltage and high power. And perhaps one advantage here is that large voltages don’t like small geometries, so old fabs can possibly get a new life.

contributed by Laura Tomkins

When a new game comes to market, the typical picture one sees is stores with lines out the doors, people camping outside the night before its release, and anxious teenagers waiting to get their hands on the new World of Warcraft Expansion.  What the companies see is sales, income, but most importantly profit.  The spotlight is on the consoles, the game and even the latest logic chips and graphics cards. But chugging along (and reaping the same good results) are the companies providing chips like power management. Critical to success, but not nearly quite as sexy.

The semiconductor market has been competing hard for these slots in the latest graphics cards.  But there is one company that can be seen within a lot of the latest models, Volterra Semiconductors.

Within the past year, Chipworks has torn down just about all of the latest high end graphics cards and within each card, they have noticed the Volterra Semiconductors signature.  But how is it that Volterra is winning so many sockets?

At Volterra’s first quarter earnings conference call on April 21, 2008, president and CEO, Jeffery Staszak stated that the, “bookings came in strong for the [first] quarter across all areas and as a result we are well-positioned, from a backlog standpoint, going into Q2. Our inventory increased due to strategic builds we made in anticipation of the ramp in both graphics cards.”

After receiving great demands for the newly designed power chips in Q1, Volterra took a risk of preparing for similar demands within the second quarter.  While notebooks and graphics cards are the two fastest growing markets in which they focus (they also sell power semis for servers), they decided to swing a lot of their resources into the graphics cards, which made an enormous leap in their revenue during the first and second quarters.

“Our Gen-5 products are also being well accepted in the graphics market as the powered delivery requirements continue to become more demanding for these high-performance graphic card applications. We have design wins with both AMD and NVIDIA on their enthusiast refresh graphics cards. As mentioned earlier, we received orders and shipped product in Q1 for the launch of AMD’s 3870X2 and NVIDIA’s GeForce 9800GX2 dual GPU cards,” mentions Staszak.

What is it about Volterra’s devices that are so popular? 

According the Staszak, Volterra believes that the ability to manage large swings in voltage and current demands within a small package is the main feature that is most appealing to graphics card companies, such as AMD and NVIDIA.  Volterra devices enable a lot of space savings while also, with the release of the Gen-5 products, deliver better performance than previous models. Chipworks’ teardowns have confirmed that the Volterra devices have resulted in fewer overall chips on the board by bringing a lot of functionality on chip. We have also seen that many competitive devices continue to use conventional lead frame, wire bond technology.

Each video card that Chipworks has torn down contained 6 to 7 Volterra devices.  While enabling better performance and more space, each card can hold more devices, with each one of them selling for $2 to $3. 

According to data provided by ATI Technologies, Inc. and Advanced Micro Devices (AMD), the total available market for graphics cards these days is about 263 million users.  The breakdown of this consists of 197M casual gamers, 52.6M mainstream gamers, and 13.15M enthusiast gamers.

Volterra has beaten other semiconductor companies such as Analog Devices, Maxim Integrated Products, and Texas Instruments to this slot. 

If Volterra’s predictions hold true for the upcoming quarters, then we should be seeing them skyrocket past the competition.

HP Returns to its Roots with the new HP 60 Printhead

Contributed by St.J. Dixon-Warren and Tim White

Hewlett-Packard is returning to it roots with the new HP 60 printhead, which features 2006 die markings. This printhead is fabricated using a similar manufacturing process seen by Chipworks in 2001 for the 600 dot-per-inch (dpi) HP 23 (C1823D) printer cartridge. That device was fabricated using a two metal NMOS technology, featuring ~4 µm transistor gates. The die size was 8.65 mm x 7.81 mm. The HP 60 (CC643WN) is also fabricated with a two metal process, but features ~3 µm gates, with a 4.18 mm x 11.49 mm die size. More importantly, HP has decided not to use their well publicized Scaleable Printing Technology to fabricate the microfluidic layers on the HP 60 device. Rather, they have returned to the use of a palladium plated, nickel metal nozzle plate.

HP 60 Ink Nozzle and Ink Cavity – Cross Section

HP 60 Ink Nozzles – Tilt View

By contrast, the more modern HP 88 printhead, which features 2003 die markings, used lithographically defined microfluidic layers composed of an organic material (likely SU-8). It is worth noting that the HP 88 was fabricated with a three metal, 1 µm process, featuring an LDMOS power transistor driving the heater resistors. The HP 88 die size is 4.39 mm x 26.05 mm. Chipworks has completed a comprehensive analysis of the Scaleable Printing Technology used by the HP 88, the HP 70, and the HPDC printheads. These printers all feature a single nozzle size, ranging from 13 - 18 µm in diameter.

HP 88 Ink Nozzle and Ink Cavity – Cross Section

HP 88 Ink Nozzles – Plan View

The process used to create the HP 60 is similar in many respects to that published in the Hewlett-Packard Journal in 1994, although they have dramatically increased the number of nozzles, from the 50 used by the HP Deskjet 500C to 1248 on the HP 60. Both the HP 60 and the HP 88 feature 1200 dpi print resolution. The HP 60 features two nozzle sizes, unlike the older technology. Clearly HP has taken their conventional printhead manufacturing process to a new level, while choosing not to use their advanced, fully-lithographic Scaleable Printing Technology for this new printhead. With the HP 60 delivering very similar specifications to the fully lithographic devices, the only reason I can think of that they chose this process technology is that the end result is lower cost, and is more suited to a disposable cartridge.

References

• http://www.hp.com/hpinfo/newsroom/press/2008/080228xa.html 
• http://h10010.www1.hp.com/wwpc/us/en/sm/WF06c/A10-12771-64199-69422-69422-69681-12785-12786.html 
• http://h10010.www1.hp.com/wwpc/us/en/sm/WF06c/A10-12771-64199-69422-69422-3564563-3564895-3565207.html 
• http://www.hp.com/hpinfo/newsroom/press_kits/2006/ipgconf/bg_scalableprinting.pdf 
• http://www.hpl.hp.com/hpjournal/94feb/feb94a6.pdf 
• Hewlett-Packard HP60 Tri-color Print Cartridge (Part Number CC643WN) MEMS Process Review with Supplemental TEM Analysis (MPR-0805-901)
• Hewlett-Packard – Canon Printheads Focused Technology Review (FTR-0703-801)

DRAMS Go Square!

Contributed by Kevin Gibb, Process Analyst

The DRAM business split some time ago into two camps: the stacked capacitor types (Samsung, Micron, Hynix , Elpida,, ProMos and Powerchip), and the trench capacitor makers (Nanya, Qimonda, and Inotera).  The trench capacitor seems to be a lonely business as Qimonda is a spin-off from Infineon, Nanya has been in a technology partnership with Infineon (or now Qimonda) that is called Inotera. Promos used to be a trench provider, but the link to Infineon dissolved a while ago.

The challenge for both trench and stack DRAM makers is to increase the packing density, and thus data density, whilst keeping the cell capacitance at a level that provides a voltage change that can be detected by the sense amplifiers.

The stack companies can keep increasing the stack height, and have done so, and they were the first to introduce high-k capacitor dielectrics to crank up the capacitance.  For the trench designers it’s a bit more difficult – they have done amazing things etching deep, high-aspect ratio trenches, but the deeper the trenches go, the bigger they are at the top, limiting how close together they can be.

To get around this, Infineon introduced bottle-shaped trenches a few years ago – the deep trenches are dry-etched, but then an oxide collar is formed at the top of the trench, and the trenches are enlarged by an isotropic etch (probably wet), giving a larger capacitor surface without a larger trench top.  That did for a while; Infineon/Qimonda got to the 90-nm generation with this process, but by the 1-Gb, 70-nm era this wasn’t good enough either.  

So the next thing is – square trenches!  Infineon disclosed square-shaped trenches, patterned in a checkerboard fashion, with hemispherical grained silicon (HSG) capacitor electrodes, at a 70 nm node, back in 2004 at the IEDM conference[1]. This was novel then, and still seems novel now, and we have been looking for it for the past few years.

Given their industry link-up, we would expect all three trench companies (Qimonda, Nanya, and Inotera) to have pretty similar process technologies for their DRAMs. And this might be the case.

We came close in 2005 when Nanya produced its 110 nm DDR2 SDRAM (Figure 1). The 150 nm by 190 nm large rectangular trenches are placed in the same X-Y grid as the wordlines and bitlines. The capacitor dielectric was made with a bilayer of oxide and silicon nitride.

Figure 1 Nanya 110 nm DDR2 SDRAM Cell

We have had to wait until now to find the IEDM ’04 structure, as DRAM manufacturers have only just started to release their 70 nm and smaller DRAMs to the market. Qimonda has adopted the checkerboard trench pattern for their 512 Mbit (and presumably 1 Gbit) GDDR5 SGRAMs (Figure 2).

The wafers used to make these DRAMs have been rotated 45^o so that the trench sidewalls are the (110) silicon planes, and are packed quite tightly. The Qimonda cells are about 150 nm x 150 nm, about 20% smaller than the 110 nm node cell shown in Figure 1. But the new DRAM cell is about half the size of the former, so a significant improvement in silicon utilization.

The trench sidewalls also have a lobed structure, which is due to the hemispherical grained silicon that provides a much increased surface area for the capacitor. This, along with Infineon’s disclosure of atomic layer deposited Al₂O₃ capacitor dielectric, should give a big boost to the cell’s capacitance. A bigger cell capacitance, and reduced bitline resistance are two ingredients for a fast DRAM.  And this may be part of the solution to Qimonda’s impressive 5 Gbps/pin data rate for the device.

Figure 2 Qimonda GDDR5 SGRAM Checkerboard Cell Capacitors

 These chips are currently in our lab, being taken apart and examined, as I write. So we hope to have Qimonda’s process and circuit designs revealed in the very near future.  We should have a few fascinating pictures to post in the not-too-distant future!

References
[1]  J. Amon et al. “A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70 nm technology” IEDM (2004) pp73-76

Lies, Damn Lies and Conference Proceedings

By Dr. Sinjin Dixon-Warren

Lies, Damn Lies, and Statistics…the inspiration for the title is a little cliché, and maybe even a slight exaggeration, but I have long been looking for an excuse to use that phrase in a blog. Let me start out by saying that one of the amazing things about our industry is that we are so open about our respective basic research. However, in the occasional case, what is presented at conferences is actually quite different than what ends-up in commercial production.

Recently, in our analysis of the Bosch SMG070 we read that Bosch encapsulated in the MEMS sensor in a vacuum (1, 2). Despite this published information we decided to proceed with residual gas analysis of the gases in the MEMS cavity. We found hydrogen with a pressure of 3-5 torr. Not to cast any dispersions on the good people at Bosch. This case is undoubtedly one where the data presented was based on a real and functioning device; one that was probably a pre-production or R&D version. It is however, a great demonstration that sometimes reverse engineering reveals surprising differences between what is released at a conference, and what companies ultimately deliver in their commercial products.

An intriguing question is whether the hydrogen in the cavity is intentional or is an accidental consequence of the device fabrication or cap attach process? Gases are often added to the cavity of inertial sensors to provide gas damping of the MEMS structures, for example as described in a recent Analog Devices Patent (3). Given the low molecular weight of H₂, and hence low gas viscosity, I suspect that the hydrogen does not provide much fluidic damping to the MEMS structure, and thus the few torr of H₂ gas does not significantly affect the performance of the gyro.

Bosch SMG070 MEMS Gyroscope Cavity

1) R. Neul, et al., Micromachined Gyros for Automotive Applications, IEEE Sensors Journal, 7 (2007) 302.
2) U.M. Gomez, et al., The 13^th International Conference on Solid-State Sensors, Actuators and Microsystems, IEEE (2005), 184.
(3) Geen; John A., et al., United States Patent 7,017,411.

Sony has twins, with more on the way!

contributed by Ray Fontaine, Process Analyst

In February 2008, Sony announced their initiative to launch two 5 Mp, 1.75 µm pixel generation CMOS image sensors (CIS).  We’ve done a full analysis on one and recently took a peak at the second.  The IMX024 is a 1.77 µm pixel sensor for an HD camcorder, while the IMX034 is a 1.75 µm pixel sensor for a camera phone (Figure 1).

Figure 1 – Sony 1.77 µm and 1.75 µm pixel size sensors

I’ll talk about the twins in a minute, but first it is worth mentioning the CIS pixel roadmap.  Recently we’ve seen 1.4 µm pixel CIS products announced from Aptina, OmniVision, Kodak, and Samsung.  While no official announcements have been made, companies such as STMicroelectronics have successfully demonstrated pixels at these dimensions.  In Figure 2, Sony indicates that they too have a 1.4 µm pixel system-on-chip (SoC) sensor in production.

Figure 2 – Sony 1.4 µm Pixel Production

So we can see where the innovators are going, but I would like to now talk about the waypoints on the journey to the 1.4 µm pixel.  As always, it helps to follow the money.  Designing smaller pixel sensors with increased performance is a costly endeavor.  Remember the days of building a CIS using a mature process line?   Well, there is a general correlation between pixel scaling and the need for a more advanced technology generation for production.  Naturally there is some industry aversion to investing in the 1.4 µm pixel generation until every bit of performance is milked from existing pixel designs.

That is exactly what we saw in the sensors we analyzed in 2007.  Companies such as Micron and OmniVision underwent 2 and 3 rounds of optimizing their existing pixel architectures.  These iterations were evolutionary in nature; sharing pixels, optimizing the metals for optical symmetry, thinning the dielectrics over the pixels, etc.  These iterations were pushed out to the market as same size pixel sensors with improved performance.

This brings me back to the Sony twins.  They’ve taken the design evolution approach one step further by optimizing based on end application.  Figure 3 shows the color filter array from the IMX024.  The IMX024 is a 5.6 Mp, 1.77 µm pixel CIS extracted from a Sony HDR-SR11 HD camcorder.  The conventional Bayer patterned color filter array is scrapped in favor of Sony’s ClearVid pixel architecture.  This architecture features a 45° pixel arrangement and a 1:6:1 RGB color filter array.  The increased green pixel count equates to higher sensitivity.  This novel pixel layout does require specialized image processing to interpret the captured image.

Figure 3 – Sony IMX024, ClearVid Pixel Layout

Figure 4 shows the metal 1 patterning used in the pixel array.  This clever metal 1 layout not only facilitates all of the necessary electrical connections, but also includes dummy metal patterns to provide a nearly symmetrical back end structure. 

Figure 4 – Sony IMX024, Pixel at Metal 1

While the IMX024 is optimized to handle HD video, its IMX034 sister is bred for capturing still images in a much smaller product.  Figure 5 shows the back of the SO905iCS camera phone, home of the 1.75 µm pixel twin.

Figure 5 – Sony SO905iCS Camera Phone

While the packaging for the IMX024 wasn’t worth mentioning, the IMX034 uses a fairly elaborate camera module.  A “periscope” system is used to stuff the lenses and focusing mechanism into the phone while maintaining a reasonable form factor (Figure 6).

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Figure 6 – Sony IMX034 Module

The IMX034 uses a conventional Bayer patterned RGB color filter array.  To date we have only performed a bevel analysis of the pixel array (no cross sectioning).  Figure 7 shows the orthogonal metal 1 layout including the outline of the light pipe window used over the photocathodes.  The IMX024 also used a unique light pipe structure, but that is the subject of another blog. 

We have only presented the metal 1 layout for each, but of course both sensors use their own flavor of pixel architecture.  In short, you might call them fraternal twins.  Sony has the advantage of designing sensors for their own products and as such we see a synergy between the downstream products and pixel/module designers.

 Figure 7 – IMX034 at Metal 1

In addition to Sony’s two pronged attack at the 1.75 µm pixel generation, they’ve also announced their production of a full frame CIS for DSLR applications.  This will be a first for Sony, and will be featured in their 25 Mp “Flagship” DSLR.  We wonder if the new sensor will be an evolution of their IMX021 pixel shown in Figure 8.  This was an APS-C size sensor taken from an Alpha 700.

Figure 8 – Sony IMX021 CIS from Alpha 700

Finally, putting together this blog has been interesting timing as Sony has just announced their development of a backside illumination (BSI) sensor.  Figure 9, taken from the Sony press release, shows a cross sectional view of their planned 1.75 µm BSI pixel structure.  OmniVision recently presented their OmniBSI™ architecture, while STMicroelectronics, MagnaChip, and others have also demonstrated the technology.  While this concept is not new the application should certainly prove to be disruptive and it is great to see new solutions to the shrinking pixel problem (signal-to-noise).  Sony has been one of the top innovators in the CIS game, and we look forward to a product announcement using this exciting technology.

Figure 9 – Sony Backside Illumination Sensor 

Links used:

http://www.sony.net/SonyInfo/IR/financial/fr/viewer/Semiconductor/2007/

http://www.chipworks.com/seamark.aspx?sm=s4%3BDatedfl10%3BDeviceType17%3BCMOS+Image+Sensorfl10%3BReportCode12%3BIPR-0804-801&cw=detail

http://www.sony.net/SonyInfo/News/Press/200801/08-010E/index.html

http://www.engadget.com/2008/02/01/sony-25mp-full-frame-dslr-hands-on/

http://www.sony.net/SonyInfo/News/Press/200806/08-069E/index.html

http://www.ovt.com/data/newsreleases/english/BSI%20Technology%20launch%20release_FINAL.pdf

MEMS Microphones Grown up and Making a Living

Contributed By: Kevin Gibb and Sinjin Dixon-Warren

We first observed MEMS based microphones back in 2003 when we did a circuit analysis of the Emkay (now Knowles Acoustics) SP0103 microphone. The field seemed pretty quiet until 2007 with our teardowns of cell phones consistently yielding coil type microphones.

The situation started to change in January 2007, when we found an example in what we believe is one of the early adopters of MEMS microphones, namely Fujitsu with its F903i cell phone. In that case, we found the S575B MEMS microphone from Knowles. Adoption seems to have started in earnest sometime around the end of 2007 as the number of cell phones showing up in our labs, sporting Knowles microphones started to rise (Figure 1 and Table 1).

Figure 1 Cell Phone Models with Knowles Acoustics Microphones

Table 1 Makes and Models Using Knowles Microphones

Given the recent socket wins by Knowles; we thought it would be interesting to take another look at their microphones, in particular the SP103BE that we analyzed in 2006.

The package photographs are shown in Figure 2.  The resin reinforced fiberglass package (likely FR4) has a central cavity into which the MEMS microphone and amplifier die have been placed.  The ASIC has been covered by a gob-top type epoxy to protect it from the environment, while the Microphone die is left exposed.  The acoustic port to the outside world is seen just above the microphone.

Figure 2 Package Photographs

The microphone is made as two parallel capacitor plates, so it would seem that it would be quite sensitive to stray electric fields. Something clearly recognized by Knowles as they have lined the inside of the package with a metal film to form a Faraday cage (electrostatic shield). This metal film can be seen in the package x-ray (Figure 3).

Figure 3 Package X-Ray

The microphone itself has a quite simple design, comprising of two parallel polysilicon plates separated by a small air gap. The upper plate (poly 2) is perforated with an array of small holes(which are needed for the MEMS release etch). A solid poly 1 plate forms the bottom capacitor plate (Figure 4).

Figure 4 MEMS Microphone

One would think that replacing the coil or condenser microphone and its complex connecting wires, in favor of MEMS based microphones in surface mount packages would simplify the cell phone manufacturing, and perhaps lower their build costs. This has encouraged others to enter the MEMS microphone business, including MEMSTech, Infineon, Akustica, Sonion and others, in addition to Knowles who presently, according to Yole Developpments, dominate this market space.

contributed by Dr. Sinjin Dixon-Warren

As part of our ongoing interest in MEMS devices, Chipworks is participating in the 2008 Hilton Head Solid State Sensors, Actuators and Microsystems Workshop as a Corporate Sponsor. While we get all the altruistic benefits of supporting researchers and innovators in the MEMS industry, I will personally get the benefit of interacting with industry leaders in the famous collegial setting of Hilton Head. A number of companies including, SiTime, MEMSIC, Kodak, Hewlett-Packard, Analog Devices and Bosch will be presenting at Hilton Head and I am looking forward to hearing what they have to say about their next generation products, and explorative Research & Design. It is also impressive how the organizers of the conference were able to get such a nice cross-section of MEMS technologies on the agenda.

SiTime will be presenting the development of ultrathin packaging for the MEMS oscillator devices. It will be interesting to understand where they are taking in their existing industry-leading technology. It is likely that the ultrathin packaging is part of their strategy to target the consumer electronics market, especially mobile devices.

SiTime SiT8002AC Silicon Oscillator

MEMSIC will be presenting results on the development of a three-axis accelerometer, based on their novel thermal convection technology. We are currently looking at this device, reportedly fabricated at TSMC on a high volume process.  So far, it is certainly very interesting physically and I am itching to find out the engineers viewpoint on the benefits of this technology versus capacitance-based devices. I am especially hoping for some performance comparisons and some interesting discussions about the benefits of an accelerometer than can handle 50,000 g’s.

MEMSIC MXD6125Q thermal accelerometer

Gilbert Hawkins of Kodak will be giving an invited talk discussing the application of instabilities in microfluidic jets in digital offset-class ink jet printers. One would think that instabilities are undesirable, so if Kodak are actually using them to enhance inkjet printing, it could be a new tweak on the technology.  We actually looked at a 6J2032 Printhead last year, so we could learn a bit more about the detail of its operation from this paper – microfluidics is not exactly our specialty.

Kodak 6J2032 Printhead Heaters and Power Transistors

Hewlett-Packard (HP) is presenting three papers, plus the Biomedical Application session is being chaired by Peter Hartwell of HP. The first concerns the use of a microlens scanner in optical interconnect, the second concerns viscous damping of a MEMS device in a cavity, and the third concerns direct printing of PZT (lead zirconate-titanate) films. The range of these papers demonstrates the continued depth of Hewlett-Packard research, suggesting that this is a company worth watching.  The viscous damping paper could shed some light on the contents of the closed cavity that MEMS is placed in.  We usually analyze the gases therein, and sometimes it’s a bit of a mystery why they are there – one part had a mixture of sulfur dioxide (SO₂) and moisture, which is quite an acidic environment.  I know SO₂ is used to preserve wine, but in a MEMS?

Hewlett-Packard C9381A HP88 Printhead Microfluidic Layer

Not to leave out the poster sessions, which often have nuggets of gold that don’t make it to the conference proceedings. I’m looking forward to Analog Devices’ poster concerning the use of extrinsic gettering in SOI wafers in their MEMS fabrication. Until recently ADI’s iMEMS process did not use SOI, however, they have recently announced the use of SOI for their ADXL001 product.  The interest here is both ADI’s migration to SOI substrates, and the nature of the gettering process.   According to a recent Yolé report, the MEMS industry is going to take an increasing proportion of the thick SOI wafer production, so I guess we can look forward to more SOI-based MEMS.

ADI’s Stephen Bart, with Hermant Desai of Freescale, will also be co-chairing the Characterization session. As a Characterization specialist myself, I am particularly looking forward to this session, which kicks off with Gilbert Hawkins’ microfluidics paper.

Analog Devices ADXL330 Accelerometer Detail - No SOI!

Freescale MMA7455L 3 Axis Accelerometer

Last, but certainly not least, Bosch will be presenting both a paper and a poster on the subject of MEMS resonators. The paper discusses charge observations in MEMS resonators – we may have mostly solved charge problems in CMOS, but we are still characterizing it in the MEMS biz.  The poster is on mode matching in high Q gyroscopes.

Bosch is not only one of the grand-daddies of this industry, having developed the critical patented Bosch Etch DRIE technology (US Patent US5501893, 1996), but they also continue to deliver innovative products, particularly in the inertial sensor market space.

Bosch SMB380 3 Axis Accelerometer Detail 

So, despite the attractions of the location, it should be a fascinating few days; and if there are quiet spells, it leaves me with time to reflect and take in the sea air.

2008 - the year of the through silicon via (TSV)?

By Kevin Gibb

The market is abuzz with talk of TSVs, with market researchers, reverse engineering companies, consultants, and just about everybody on the hunt for their implementation in products.

Through silicon vias are a long time in coming; as one of our own engineers was involved in a TSV project some 11 years ago, and at that time it was deemed to be too difficult to make commercially viable and cancelled. Hopefully all of the noise we are hearing from manufacturers won’t take another 11 years (or even months) to happen.

The argument for TSVs is now compelling, as device integration and technology node shrinks are forcing engineers to consider 3D integration for some device sectors. We think cell phone CMOS image sensors will be the first to market with TSVs, followed by memories. Both get cost benefits on highly repetitive structures and both have been publishing papers, patents, and press releases faster than you can say, “wafer scale packaging”.

CIS will very likely precede NAND or DRAM since technical requirements on the TSV's will be less stringent for CIS packaging. Memory will be very close behind (probably Samsung) since they are investing more in development and reap better overall benefits as a percentage of the total cost of manufacturing. Chipworks' bet is on Toshiba delivering an image sensor, because they already claim to be in production with a VGA CIS with TSV's. However, it has not shown up in a downstream mobile phone yet.

With this in mind, we thought it a good time to take a look at some of the interesting multi-chip packaging that we have seen that help to get us to this point. The two good reasons for this are because it helps illustrate some of the challenges, but also because the images are just, well, cool.

A few years ago a Sharp device came out with a five stack chip scale package containing three flash and two SRAM dies stacked one on top of the other. The full package measured 8mm x 11 mm and only 1.13 mm thick. To a large extent this was achieved by thinning the dies down to an average of 95 µm thick each. This seems quite impressive as many single dies are still, even today, packaged with a 200 to 250 µm thickness.

Figure 1 Sharp 5 Stacked Chip SRAM & Flash Memory

Sharp was not alone with this strategy, as Fujitsu was also offering a multichip package having two flash, an SRAM and DRAM dies in a 11 mm x 12 mm by 1.1 mm thick package. Again thinning of the dies was in order, but to only 130 µm thick in this case. We also note the horizontal approach of the wire bonds to the top die (die 4).

Figure 2 Fujitsu 4 Stack Flash, SRAM and DRAM Memory

The wire bonding to the dies has also been modified to allow a near horizontal approach of the bond wires to the die. This permits a reduced loop height for the bond wires and consequently a thinner package. A seminal development for wire-bonding multi-stacked dies has been the ability to reverse the direction of the wire, first placing a stub ball bond on the die, then wedge-bonding the wire on to that.

The most remarkable example we have seen so far was in a Sandisk 8 GB memory which also had a five-stack (four 2 Gb/16 Gb die + a spacer) structure. As you can see we have a stub bond on the top die, with a wire wedge-bonded from that to a ball bond placed on a wedge bond from a lower wire, on another stub on the die below. And these bonds were on a die thinned to a remarkable 65 μm, and hanging out 750 μm beyond the spacer below!

Figure 3: Sandisk 8Gb Bonding

Real estate is still expensive in cell phones, with a push to shrink the footprint for every IC being used. One strategy for achieving this is to dispense with the bond wires and use some form of chip scale package interconnects.

Shellcase did this almost a decade ago with their chip scale packaging for CMOS image sensors. This approach puts the package interconnects on the backside of the die, so that the entire package can be flip-chip bumped to a printed wiring board. This approach seems successful as OmniVision has adopted this approach for their OV2640 CMOS image sensors being used and Sony Ericsson's V630i mobile handsets. In this case XinTec appears to have provided the packaging for OmniVision.

Figure 4 Chip Scale Package for a CMOS Image Sensor

And this leads us to the next idea for reducing the package size, and that is to use TSVs. The idea is to allow dies to be stacked one on top of the other, with the interconnects feeding from one die to the next through stacked die vias.

Of course the GaAs guys are probably wondering what all the fuss is about, as they have been producing die with TSV’s for the past 10-15 years. With GaAs being an insulating substrate they are needed to ensure a good ground plane and to remove heat from the die. The example below from Philips is a GaAs HBT power transistor contained in a small GSM power amplifier. The GaAs has been thinned to about 75 µm thickness, after which the 70 µm wide vias have been etched from the backside. As is normal with GaAs TSVs, the vias are plated with gold.

Figure 5 Through Hole Via in Philips GSM Quad Band Amplifier

Whether TSVs show first in CMOS image sensors or memories, we can be sure that they will be leveraging the work that the MEMS industry has done in dealing with deep-etched silicon structures. TSV’s will almost certainly be etched with some derivation of the common “Bosch” etch process. A paper at this weeks ASMC conference from Puech et. al. of Alcatel Micro Machining Systems gave a good description of the etch technology required for TSV. We have an example below from SiTime, which has used a Bosch etch to form the ring of trench isolation (annulus) surrounding the polysilicon via shown in Figure 5. Not quite a TSV but certainly a very deep silicon via relative to the width.

Figure 6 SiTime Polysilicon Via

Intel Atom to be Analyzed

Contributed by Dick James, Senior Technology Analyst

Chipworks has the Intel Atom processor in our labs, and we will be looking at it in detail over the next few weeks. Since Intel has announced [1] that it is made with the same process [2] as the Penryn, we will be looking for differences rather than doing the type of exhaustive analysis that we did on the Penryn.

We will be looking first at the front-end processing and the dielectric stack to confirm the high-k/metal gate structure. We’ll also examine the interconnect stack, the SRAM cell layout and size, and logic cells – in other words, anything that could contribute to the low-power designation of the chip.

Just looking at the chips as we received them, it’s obvious that they are low-power parts – no honking great heat spreader such as we saw on the Xeon version of the Penryn. The Atom is on the left below; of course the scale is different, since the Xeon package contains two 105 mm² dice on a 37.5 x 37.5 mm board, whereas the Atom is ~25.5 mm² on a 13 x 14 mm substrate.

The first thing I wondered, when I heard that we had the Atoms, was whether the thick copper redistribution layer (RDL) used in the Penryns was still used. After all, low power means reduced current, and if the current is reduced, is a thick copper layer needed?

The first sight of the naked chip cleared that up – see the die photo below. If you squint hard, you can see what look like micro-tracks, which are actually the gaps between the wide redistribution lines.

We can see them more clearly in the die marking image:

This RDL is ~6.5 µm thick, and appears to be electroplated on to a thin Cu seed layer. This is from our Xeon report:

According to Intel, this layer is used for improved on-die power distribution, which in a part that dissipates ~2W rather than >60W seems a bit like overkill. On the other hand, there will be side benefits such as good thermal redistribution across the die, and having these thick, wide copper tracks on the chip surface must help the layout and alignment of the copper bumps used by Intel these days to connect to the outside world. This is what the stack looked like in the Xeon:

We’ll comment more on the Atom itself when we’ve finished the analysis.

In the meantime, Digitimes speculates that Asus has ordered 2.5 – 3 million Atom chips from Intel for the new version of the Eee to be launched in June, and Acer has ordered another million.

Via Technologies also seems to be getting a boost from interest in mobile PC chips – HP is reported to have ordered ~100k Via C7-M low-power processors for its HP 2133 Mini-Note PC. They also got a boost from a German Eee website with a comparison test showing that the new Via Isaiah chip handily outperforms the Atom.

We’ll see what happens with the Atom – there is viable competition out there, and it is likely to increase, as the mobile internet is perceived as the growth market for the next few years.

[1] G. Gerosa et al., A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-κ Metal Gate CMOS, 2008 IEEE International Solid-State Circuits Conference, pp 256-257.

[2] K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, 2007 IEDM Tech. Dig. pp 247-250.

Winter is finally starting to fade in Ottawa, after one of the snowiest winters in memory (the first white Easter in my time here!), and the early signs of spring are showing. The maple sap is running, the first migrant birds have arrived, the frogs are peeping, and we have evening daylight. On the conference calendar, spring means that ASMC (Advanced Semiconductor Manufacturing Conference) is on the horizon, this year in Cambridge, Massachusetts. There, spring in early May should be well advanced, and it will be a great time of year to visit New England.

As the name says, ASMC is an annual conference focused on the manufacturing of semiconductor devices – in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers.

I’m plugging ASMC because it seems to be one of the more under-rated conferences, unlike IEDM and the VLSI symposia which get the media attention for leading-edge R & D and processes. However, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.

I always come away impressed by the quality of the engineering involved; not being a fab person myself any more, it’s easy to get disconnected from the density of effort required to equip a fab, keep it running and bring new products/processes into production. Usually the guys in the fab only get publicity if something goes wrong!

This year there are more than 80 papers, with keynotes from AMD, IBM, Intel, Linde Electronics and Synopsys. Sessions include:

• Advanced Metrology
• Advanced Processing
• Advanced Equipment and Materials
• Contamination Free Manufacturing (CFM)
• Cost Reduction, Equipment Reliability and Productivity
• Defect Inspection and Reduction
• Design for Manufacturability (DFM)
• Factory Automation and Dynamics
• Lithography Advances
• Yield Methodologies.

Of course, I’m biased to some extent because I’ll be giving a paper there – “From Strain to High-K/Metal Gate – the 65 – 45 nm Transition”, essentially a review of transistor structures from the 65-nm generation through to the Intel 45-nm chip. This will be the fourth year running I’ve given a paper there, the manufacturing and equipment engineers that attend seem to like seeing what other companies are doing.

Last year we also had a good range of topics - there are a lot on esoteric (for me, anyway!) stuff such as fab loading algorithms and yield modeling, but there are also nuggets of information in the processing area.

An interesting bit of diagnostic work that stuck in my mind was an instability in voltage references in a SOI-based microprocessor caused by mobile charge contamination [1]. The process includes tungsten local interconnect, and of course the interconnect trenches were cut through the CESL nitride; however, where these openings overlap onto isolation oxide, there are entry points for mobile ions, which can then migrate into the buried oxide underneath a transistor, affecting the body potential.

Apart from removing the cause of the contamination (not easy with some process steps!), the mechanism can be eliminated by keeping the tungsten over active silicon. This problem struck a chord in me, mainly because it was something that I hadn’t thought about, but is quite logical since SOI devices are by definition surrounded by oxide.

We tend to forget that mobile charge was the curse of MOS technology in the early days, to the point that people weren’t sure that it could be made to work at all. Bruce Deal wrote a great review paper of the problems way back when in ’74 [2], and he included this telling cartoon by Bob Donovan that aptly summarizes the confusion that existed before we finally got a handle on the different types of oxide charge.

I guess I drifted a bit off topic there, since that was a bit of a trip down memory lane, and not much to do with ASMC – but if you’re in the market for real-world fab information, compared with R&D exotica, come to Cambridge next month. I look forward to meeting you!

[1] M. Connell et al., “Impact of Mobile Charge on Matching Sensitivity in SOI Analog Circuit,s” Proc. ASMC 2007.

[2] B. E. Deal, “The current understanding of charges in the thermally oxidized silicon structure,” J. Electrochem. Soc., vol. 121, p. 188C, 1974.

Moving all that Image Sensor Data off the Sensor Array Ain't Easy

Contributed by Mike Christie, Circuit Analyst

Our process readers will find this latest blog a little off their expertise. However, circuit analysis is a very significant part of reverse engineering. With this in mind, we will explore the huge increase in complexity that we have seen in circuitry for CMOS image sensors (CIS). Gary Tomkins’ blog a couple of weeks ago briefly mentioned the information processing power we have seen in the latest DSLRs. But all of that data has to get off the image sensor first, and that is driving evolution in the sensor design.

Chipworks has seen a trend in CMOS image sensor devices wherein the designers have moved away from large, stand-alone pipeline analog to digital converters (ADC) to integrating single-slope ADCs which are in-line with the pixel array and contain an ADC for each column of the array. This architecture is now being adopted by companies such as Sony for the IMX017 who in the past have relied on the pipeline architecture. The obvious benefit is that data can be moved off the sensor at high bandwidths. A second benefit is that each ADC has much longer to operate on a single sample, thus allowing longer settling times, lower noise, and higher accuracy.

Let’s look at the column ADC architecture on the Sony IMX017 (Fig. 1). Each column from the pixel array is connected to a comparator circuit, which compares the output data to a high-precision staircase reference voltage. The output of these comparators is in turn connected to a counter which will latch the count when the reference voltage reaches a level at, or above, that of the column output data.

This architecture is hailed as the latest innovation in CISs. However, Chipworks has already analyzed a number of devices using this design methodology. With the IMX017, Sony have also adopted this next generation architecture. In fact, this design is already undergoing innovation from the early devices. Samsung’s image sensors are a good example.

The latest Samsung CIS (S5K4G1X) is their 2^nd generation using a column ADC architecture. Chipworks has found a significant design innovation within the in-column ADC design as compared to their previous designs. For instance, Samsung’s previous S5K4BAFX ramp generation DAC used a resistor string voltage divider (Figure 2). Their latest generation uses a current steering DAC.

For the in-column ADC architecture, the creation of a precise staircase reference voltage is necessary for use in the comparator array. Typically, this type of voltage is generated using a digital to analog converter (DAC). For 10-bit ADCs, this DAC has been based on a resistor-string architecture while the latest Samsung, which boasts a 12-bit ADC, uses a current-steering DAC.

This is a significant step, as current steering DACs are much more complex and costly to implement. For a 12-bit ADC, it is apparent that the need for precision in the reference voltage is great enough that the cost and additional space of the current-steering DAC is required.

(click for printable jpg)

Figure 2: An example of a portion of the resistor string DAC in a previous generation of Samsung’s CMOS image sensors (S5K4BAFX) from the fine voltage divider. This is a standard design, using a large resistor string feeding a number of switches that in turn are controlled by a digital input bus driven by a fully decoded counter. This digital bus selects a particular output reference voltage to supply to the comparators.

(click for printable jpg)

Figure 3: A segment of the current-steering DAC from the Samsung S5K4G1X CMOS image sensor. Each current generating element consists of three transistors and a 5-bit decoder. A 14-bit input bus controls the output current.

Chipworks has witnessed the steady increase in image sensor complexity as this technology has matured. The size of the Circuit Analysis Reports for image sensors that we are delivering to our clients has increased significantly, with the average number of circuits more than doubling in the last 12 months. And this is not a linear trend line. Like any technology, innovation just does not sit still.

Figure 4: Plotting the number of schematics in an Image Sensor Circuit Analysis Report with some of the key devices shown.

Is Quartz the new Vacuum Tube?

A Look at the Discera MEMS Oscillator

Kevin Gibb

After many years living in universities as curiosities, micro-electromechanical systems (MEMS) have grown-up and are making a living in commercial devices.

To some, the emergence of silicon is a platform of choice for MEMS may seem somewhat unexpected. To us working in silicon, this is no surprise, as the semiconductor industry has a massive embedded infrastructure for silicon processing. And fortuitously, silicon and exhibits many desirable features for fabricating MEMS. It can be drawn as a single crystal or deposited as a polycrystalline material, it can have a thermally grown oxide, and is amenable to a number of etch processes.

The huge existing industry based on silicon means that processing tools are readily available.

A number of MEMS devices lend themselves to mass production, and the ability to scale down in size, so we are not surprised to see a number of commercial devices emerging, such as: accelerometers, gyroscopes, microphones, and now oscillators.

Oscillators are a bit of curious beast, as resonator structures are often made from single crystalsilicon or polysilicon beams, which suffer from thermal expansion as the temperature rises. So they are not intrinsically stable over temperature, but engineers (being the clever people they are) overcome this by using compensation circuitry to achieve very low frequency drift. Low enough, for them to be considered as replacements for quartz oscillators in digital consumer and mobile products (cell phones, MP3 players, cameras, and TV).

Discera is one such company manufacturing silicon-based resonators. And we thought we'd take a closer look at one of their devices, the ASLM1-20.000MHz-C-T. As a side-note we are completing full analysis on the SiTimeSiT8002 MEMS oscillator that takes a very different design approach. It will be an interesting investigation to understand how the two designs deliver different specifications.

The resonator and its control ASIC are encapsulated in a small plastic molded QFN type package. We show the resonator die and its silicon cap in Figure 1. A cavity has been opened into the backside of the cap to provide space for the MEMS resonator. The cap is bonded to the MEMS die with a hermetically tight seal, and a portion of the cavity roof has been coated with a getter material to help maintain the vacuum formed in this cavity.

Figure 1: Resonator Die and Cap

We have removed the silicon cap from the resonator die in Figure 2. Remnants of the lead glass seal material can be seen on the die. The resonator structure is located near the middle of the open portion of the die.

Figure 2: Resonator Die

The resonator is shown in Figure 3. This looks to be a rectangular polysilicon proof mass supported by thin beams at the four corners. Two electrodes are seen beneath the resonator, with the one contacting the polysilicon resonator plate, and the other serving as an opposing capacitor plate on the die surface.

The DC bias and in AC excitation signal would be applied to the resonator to cause it to resonate in the vertical direction. The Q for this resonator is highly sensitive to the pressure within the cavity, which is likely kept below 1x 10^-4 Torr. And this would explain the need for the getter compound on the inside of the cap.

Figure 3: MEMS Resonator

Both silicon and polysilicon have mechanical properties that change with temperature. So without some form of compensation, the resonant frequency will shift with temperature. And this brings us the forward biased diode, which can be used as a temperature sensing element. We don’t see it on the resonator die, so it must be on the control ASIC that is packaged together with the resonator.

A correction signal can be derived from this, to either adjust the DC bias being applied to the resonator, or one can use this signal to adjust the frequency output of a phase lock loop type oscillator circuit.

The performance of these devices is looking pretty good and may soon replace quartz crystal oscillators in many applications. This is especially so for mobile communication devices like cell phones, where space is at a premium, and the need to shrink the oscillator is compelling. MEMS structures offer the opportunity to scale, whereas quartz oscillators tend to be fixed in size.

We may soon look back at quartz oscillators the way we do vacuum tubes. A technology, while important in its time, has passed the torch onto the new new new.

DSLR Sensor Economics

By Gary Tomkins

We look at a lot of image sensors at Chipworks. It’s an interesting area, the state of the art is constantly evolving, and every sensor has unique features. The market is primarily driven by the mobile phone demands, but the digital camera is an attractive market on its own with over 100 million cameras shipped in 2007 and has been experiencing 20%+ annual growth. The DSLR (Digital Single Lens Reflex) camera is the fastest growing segment with an expected 9.1 million units shipping in 2008. (These figures come from the Camera and Imaging Products Association, CIPA here.)

DSLR cameras are now dominated by CMOS image sensors, this was initiated by Canon in 2003 when they launched the first DSLR to use a CIS, the Canon EOS 10D a 6.3 megapixel camera containing the Canon 704F CIS, demonstrating that CMOS image sensors are capable of producing the same quality images as CCD based cameras.

Now virtually all DSLR cameras contain CIS devices, driven by the need to get large pixel count data streamed off the chip quickly, and the lower power consumption of a CIS. The latest DSLR sensors that we are currently analyzing are 35mm full frame sensors from the top of line professional DSLR’s the Canon EOS 1Ds mark III, and the Nikon D3. These professional DSLR cameras contain some serious processing horsepower to get the signals out of the sensor. On the Nikon D3 we found a whopping 6 total Analog Devices AD9974 signal processors – presumably two for each color.

PCB in Nikon D3 DSLR

For the Canon – they are employing two of their Digic III Image Processors to handle the massive volume of data that a 21 megapixel camera can be imaging at five frames-per-second.

PCB in Canon EOS 1D Mark III DSLR

Interestingly Canon and Nikon, whilst both settling on CMOS sensors are diverging in their application. Canon with a whopping 21.1 megapixel sensor are driving resolution, whilst Nikon have chosen to use a 12.1 megapixel sensor, and have traded the bigger pixel area for increased sensitivity, (The Nikon D3 has an amazing ISO200-6400 sensitivity range in normal settings.)

What makes these sensors very interesting is the 36mm x 24mm full frame format. The majority of DSLR cameras use a 22mm x 15mm APS-C size sensor. To the photography enthusiasts the 1.6X multiplier that is required to image down to the APS-C format is a significant limiter to picture quality. Many expect the APS-C format to be a temporary stage, before all DSLR cameras are manufactured with full frame sensors. An excellent article on this, written by Bob Aitkins can be found here. Although for performance the full frame is clearly desirable, I think it will be a huge competitive challenge to provide this at the consumer or “prosumer” or hobbyist level.

These full frame sensors with ~6-9µm pixel sizes are fabricated with fairly relaxed design rules (~0.35-0.5µm ) compared to the current state of the art mobile phone sensors (Which are fabricated with 130 nm or even tighter 90 nm design rules). However there are challenges with sophisticated backend processing, and stringent junction leakage requirements and the low defect densities required to yield the required pixel performance.

Full frame sensors also present a unique challenge due to the die size being larger than what a normal lithography stepper is capable of printing. Current steppers from ASML, and notably Nikon and Canon typically have a 26 mm x 33mm maximum field size, large but still smaller than the full frame 24mm x 36mm requirement. To overcome this requires ‘stitching lithography’ where separate reticles (Stepper masks) each containing a portion of the die are exposed in serial fashion. This not only increases lithography costs due to the multiple steppings it is inherently difficult to ensure the on-die alignment needed.

Artifacts of stitching seen on Nikon D3 Sensor

Canon appears to be the only lithography equipment manufacturer to offer an i-line stepper configured for 200/300mm wafers with a 50mm x 50mm field. It is only capable of ~0.5µm design rules, but that is consistent with the geometries seen on the Canon CIS we are analyzing. We have not seen any evidence of stitching in the Canon device, thus if they are using this stepper in their CIS manufacturing line, they likely have some cost advantages over the D3 foundry.

The foundry for the Nikon D3 sensor is an interesting sidebar topic. Nikon have announced that they designed the sensor. Nikon has no wafer fabrication capability so they outsource the sensor production, but they are keeping the foundry close to their chests, so close that we must speculate to identify the source.

Die Markings on the image sensor found in the Nikon D3 DSLR

The obvious choice would be Sony, who build the sensor used in the Nikon D2X, however there are no Sony markings on the device, and the device structure is markedly different from the other Sony CIS we have analyzed. We considered Matsushita/Panasonic the device structure has similarities to the Panasonic CIS we have seen, but it is sufficiently different that we have doubts that it is theirs. Thus we are speculating who else could be the manufacturing source. I believe Nikon would stick with a Japanese foundry. An interesting possibility is Renesas, they have close ties with Nikon, supplying several imager processor chipsets, they have a patent portfolio in image sensors indicating they have active r+d in this field, and they have the fab capabilities. If indeed they are the foundry source for the D3, it makes them an interesting new entrant into the CIS manufacturing world.

 The consumer/prosumer cameras now span the $500-$1500 price range, the latest full-frame sensor DSLR’s span the $5000-8000 range. For the full frame sensors I believe achieving a average 50% yield would be impressive (One thing for sure the semiconductor manufacturers will not be disclosing what their die yields are, that is always the most closely guarded secret.) Thus I speculate with probing and packaging (These die justify a very expensive ceramic package) the cost to manufacture these sensors to be ~$300-400 each, compared to ~$70-80 for an APS-C sensor. Without the luxury of die shrinks available to reduce costs I believe it will be a long time before we see the full frame sensors on sub $1500 cameras. (But I would like to be proved wrong.)

Spotlight on Sony - Comparing three image sensors designed for different applications

Sony has long been a market leader in the CMOS image sensor market by both out-pacing the already robust growth in the market and by continually releasing innovative new technology. This includes devices designed with the smallest footprint for camera phones up to the most advanced digital SLR’s (DSLR). The former category is one characterized by a race to the smallest footprint, the lowest cost, and the lowest power consumption, the latter, in driving price, performance, and usability to a level where you can deliver amazing quality at a consumer, sub-$1,000, price point.

To explore this we are going to focus on three products from Sony, the IMX017 for camcorders, the IMX020 for cell phone cameras, and the IMX021 for DSLRs. This provides a broad look at Sony’s innovation, but with a unique advantage of providing technical depth to the analysis. This will show how Sony’s investment in R&D has resulted in products that are technically differentiated for related applications. The full story, of course, is in Chipworks detailed reports on these devices.

The jaded consumer, or even OEM, may believe that inter-generational devices and generational shrinkages generally only have minor tweaks and that it is just the marketing team who builds a convincing “pitch” for a smaller pixel, more resolution, and better performance. It turns out that, in Sony’s case, nothing could be further from the truth. The designs differences include process and circuit innovations that are tailored to the application.

Process hints lead us to believe that the IMX017 is a slightly earlier design than the other devices. However, the IMX020 has the same, 2006 date code on the die markings as the IMX017 so this conclusion may not be correct.

The IMX017 is the first Sony image sensor that Chipworks reported on that uses a column ADC (Samsung, Toshiba, and STM have used column ADCs for a while now). Sony made a big splash about this architecture change because it allowed the very fast video rate at full resolution – giving good resolution and the ability to take some interesting video (at that rate you can take slow motion video).

Preliminary analysis on the IMX020 and IMX021 (the images have only just come out of the lab) suggests that the IMX021 column and DAC layout is different from both the IMX020 and the IMX017. Because the IMX021 is a 12 bit column ADC just like the IMX017, we would expect the same column and DAC architecture. However the layout is different. It is either a ‘next generation’ column ADC design or a application specific design.

The IMX020 has 5 Mp resolution, but is targeted for cell phones. Different than the IMX017, it squeezes 78% of the IMX017 pixels into 69% of the area and it also employs a column ADC but it has been refined. The column and DAC layout are also different than the IMX017. The end result is that this device should be quite a lot less expensive to produce and still deliver image quality needed for a cell phone.

Images of the DAC also suggests that the design is quite different between the devices. Further analysis is underway as part of the Circuit Analysis Reports to confirm this. However, the general trend is that each has a different level of complexity based on the need to generate good SNR and enable a fast frame rate.

In conclusion – three image sensors from Sony all suggesting rather significant differences in design. No different than needing to understand the difference between an advanced node process for raw speed and for low power consumption is the need to understand the very real design trade-offs within generations for image sensors. These devices suggest real differences in circuit design for different applications. It isn't all just marketing spin after all.

Dick James, Senior Technology Advisor

Last week we looked at the lithography improvements in gate patterning, particularly in the SRAM array. This week let’s take a broader look at other improvements in lithography and layout seen in the 45-nm process, since Intel has stayed with dry exposure when others are moving to wet lithography tools. Table 1 lists the pitches of the different levels that we found in our analyses.

Table 1 Pitch Measurements in Intel Xeon and Yonah

Figures 1 – 4 show images of the SRAM array from the Xeon (left), and the 65-nm Yonah chips, going down from the metal 3 (M3) level to the gate level. At all the metal levels we can see that, contrary to intuition, the edges are much crisper and line edge roughness is reduced. (In the Xeon-M2 sample, there has been some movement of the lines due to our sample prep.)

Figure 1 Plan-View SEM Images of M3 Level in Intel Xeon and Yonah

Figure 2 M2 Level in Intel Xeon and Yonah

Figure 3 M1 Level in Intel Xeon and Yonah

Figure 4 Gate Level in Intel Xeon and Yonah

In the gate images (Fig. 4), the edges are not as well defined, but then the sidewall spacers are also present – we cannot see the actual gate edges. The tungsten M0 level is also present in the Xeon sample to add to the confusion. The Intel images (see last week’s blog) of polysilicon from the IEDM paper are clearer, and show similar impressive changes.

When it comes to the metal levels, at M1 it seems that dual-APSM has been used (double masking as opposed to double patterning). Fig. 3 shows the “wiggle” in the V_DD line, and Figure 5 shows an area of standard cells in the logic array, with some very tight Manhattan layout in the cells. It was in these areas that we found the tightest M1 pitch, closer to 150 nm than the announced 160 nm [1].

Figure 5 Plan-View SEM of Metal 1 in Logic Area

With features this densely spaced, and using dry exposure tools, it is obviously a daunting task to define patterns without any faults, even with APSM and the most advanced reticle enhancement and optical proximity correction techniques. Dual APSM takes the hypothesis that phase conflicts can be avoided for both masks, if apertures oriented along the vertical direction are assigned to one mask, and those along the horizontal direction to the other [2]. If Intel is using dual-APSM, I think the hypothesis is proven!

At M2, we found a very limited use of orthogonal patterning, and M3 none at all; but since the pitch is still 160 nm, it is possible that dual masking was used, although the M3 masks would be oriented in the same direction.

If we look again at Fig. 5, we can see that some of the lines between the logic cells are a darker shade of grey than others in the cells. This is a function of the secondary electrons seen by the SEM detector, but for our purposes it indicates dummy metal lines used in the layout of the part. The same effect is shown (Fig. 6) at M2 and M3. In other parts of the die Intel has used dummy metal for a much greater proportion of the area, particularly at the M1 level (Fig. 7).

Figure 6 Plan-View SEM of M2 (right) and M3 in Logic Area

Figure 7 Dummy M1 and Interconnect

Of course, the use of dummy metal is almost as old as the use of CMP, but this is the first time we have seen it employed so extensively, so densely, and so early in the back-end processing. For CMP control we usually see small structures such as squares of metal– here the dummy structures are lines squeezed in at every possible position where there is no active metal needed. However, the regularity of this layout cannot but reduce the lithographic variation, and coupled with CMP improvements (Fig. 8), we get the impressive metallization seen in Figs 1-3.

Figure 8 Improvement in M1 Uniformity after Cu Etch and CMP Enhancements [3]

We also found the same layout philosophy used at the gate level. Figure 9 is an example of an area of general logic (note that the diffusions are covered by dielectric material in this image). Repetitive columns of metal gate fingers are arranged parallel to columns of M0 trench contacts. In regions where no active devices are required, these metal gate strips serve as dummy structures. Where an active device is required, the column is simply broken, long enough to form a gate finger, and continues on again beyond the device as dummy metal. In the same way, the W trench contacts can be tailored to any length necessary.

Figure 9 Gate-Level Image of Logic Area

This layout has several advantages; in addition to aiding lithography, the use of trench contacts also enables flexibility in choosing where to place a contact up to metal 1. The trenches can be routed to a region over STI to form a contact land, as opposed to being forced to contact the top of a conventional contact stud over active Si.

The trench contacts also form butted, or split, contacts enabling connection of one or several gates to one or several diffusions, without the use of a metal 1 strap. Numerous manufacturers have used butted contacts as a means to reduce the unit 6T SRAM cell size, but the Penryn die marks the first time we have seen Intel use butted contacts to increase packing density in the core logic blocks.

Intel had mentioned this “dummification” technique in a presentation at their 2006 Developer Forum [4], and in addition to the above advantages, they claim that it reduces leakage (Fig. 10) and improves thermal processing (Fig. 11). This makes intuitive sense, since more uniform metal density across the die and across the wafer should improve the uniformity of heat absorption and dissipation, and thus reduce any hot or cool spots that could affect dopant variations.

Figure 10 Performance Improvements after Dummification [4]

Fig. 11 Process Parameter Improvement after Dummification [3]

To monitor the end-of-line results, Intel designers place ring oscillators in all product designs. Performance data such as f_max can be used to identify areas of concern, and give a measure of the systematic and random variation seen in the process. Figure 12 shows the trend in f_max over recent process generations: looking at this, it is apparent even after four generations of shrinkage, variation is amazingly well controlled.

Figure 12. Trend in Systematic Within-Wafer Variation from Ring Oscillator f_max Data [3]

So to wrap up, while Intel’s process paper [1] got all the advance hype, Kelin’s paper [3] reveals an equally impressive and detailed body of work, and equally essential to the manufacturing success of the 45-nm products.

Judging by the limited sample seen in our analyses, all the work done on improving individual process steps, and using the kind of design and layout changes discussed above, paid off admirably in the final product. A true tribute to the 45-nm development and manufacturing team!

References:

[1] K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”,Proc IEDM, 2007 pp. 247 – 250; http://download.intel.com/technology/IEDM2007/HiKMG_paper.pdf; http://download.intel.com/technology/iedm2007/HiKMG_pres.pdf

[2] D. Bernard et al., “Clear-field dual alternating phase-shift mask lithography” Optical Microlithography XV, Proc. SPIE Vol. 4691, p. 999-1008.

[3]K. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”, Proc. IEDM, 2007, pp. 471 – 474;http://download.intel.com/technology/IEDM2007/variation.pdf,http://download.intel.com/technology/IEDM2007/variation_pres.pdf

[4] S. Rikhi et al., “Design for manufacturing”, IDF 2006, session EPRS008

N.B. This blog is excerpted from this months “Chip Forensics” article in Solid State Technology magazine.

Intel’s Other IEDM Paper- Part 1

Dick James, Senior Technology Advisor

At IEDM last year, there was a short course on “Performance Boosters for Advanced CMOS Devices”, and the last session of the day was given by Paul Packan of Intel, on Device and Circuit Interactions. Within this there was a discussion of Design for Manufacturability – one of this decade’s main foci for the industry. In addition to the usual details on lithographic and design rule enhancements, there were a couple of slides showing how inserting dummy devices to give a regular layout and optimize pattern density can reduce variability, and improve manufacturing parameters such as the temperature distribution across a wafer during thermal processing.

A couple of days later Kelin Kuhn gave her paper “Reducing Variation in Advanced Logic Technologies” [1], which went into more detail about some of the layout and process changes used to limit, and even improve variation in 45-nm parts compared with their 65-nm predecessors.

I mention these presentations because after seeing them, it clarified the reasons for the extraordinary differences from previous chips that we found when we analyzed Intel’s 45-nm Xeon processor last fall.

Figure 1: Intel Images of SRAM Poly (source: Intel)

One of the problems highlighted in the paper is that a 0.7x shrink in critical dimension (CD) also requires a 0.7x improvement in CD variation. Intel appears to have accomplished this by a combination of design/layout changes, and process technology improvements. The SRAM gate layout has changed drastically from the 90-nm node, going from a “tall” to a “wide” layout in the 90 – 65-nm transition, and using process mitigation and patterning improvements between the 65-nm and 45-nm processes (Fig.1).

Intel has clearly put a lot of work into improving their lithography processes for this latest generation, especially as they continue to use dry exposure. Here I use “lithography” in its classical sense, to include the etch and CMP processes – after all, if you buy a lithograph print, you buy the finished print, not the intermediate masking stage before the ink goes on the paper; and it is the final, defined features that form an IC.

Intel has stated that they use double patterning at the gate level, and dual APSM (alternating phase-shift masking) in their 45-nm processing. Design rule changes have been made at the lowest levels to minimize any orthogonal patterning – in the SRAM the only right-angle features are in the M0 local interconnect. The 45-nm test chip announced in January ’06 was used to confirm the results of the computational lithography and DFM simulations employed to co-optimize the products and process.

The squaring of the gate electrodes in the 45-nm image is presumably produced as the result of the optimized APSM and the double patterning – we have also seen this latter in the latest flash memory parts, so it is becoming an established technique. The reduced pattern variation given by the increased spacing of the electrodes at each patterning step has to be an overall benefit when compared with the increased cost of the process, and extra challenges such as controlling the overlay between the steps. The actual benefit is to reduce the variations caused by “dog-bone” and “icicle” endcaps, and this should contribute to an improvement in the cell mismatch [1].

Of course, when we analysed the new Xeon chip, we were curious to see how well the actual product compared with the sacrificial polysilicon pattern shown in Fig. 1. The SEM images cannot give us enough detail because, as a surface imaging technique, it cannot distinguish the spacers from the metal in the gates.

Figure 2 is a plan-view TEM image of a pair of combined PMOS/NMOS gates from the SRAM, and we can see that they have kept the square profile fairly well through the etch, metal deposition, and CMP steps required to make the metal gate structure. The PMOS transistors are distinguished by the mottled texture of the titanium nitride used in the PMOS gates, as opposed the aluminium fill used in the NMOS. The sidewall spacers can be seen as a faint ghosting around the gate electrodes.

Figure 2: Plan-view TEM image of gates in SRAM array

However, if we look outside the SRAM array (Fig. 3), more rounded outlines are found, so it appears that the array transistors are particularly tuned to be square-ended; which is not unreasonable, since nearly half the chip is taken up by the SRAM cache memory.

Figure 3: TEM images of metal gates

In the next part of this discussion, we will look at other lithography and design/layout changes that have contributed to minimizing the manufacturing variation and maximizing the yield.

More details can be seen in the March "Chip Forensics" column in Solid State Technology magazine.

[1]K. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”, Proc. IEDM, 2007, pp. 471 – 474;
http://download.intel.com/technology/IEDM2007/variation.pdf,
http://download.intel.com/technology/IEDM2007/variation_pres.pdf

The ITRS roadmap is off the rails - but the statistics hold the story, and memory cell size remains a good predictor of node

By Kevin Gibb

That manufacturers are not holding true to the ITRS roadmap is no big story. Sometime ago it was thought that technology nodes, as declared by foundries, did not mean very much, as the declared node did not seem to match lithographic features found on the die. This is perhaps true if one looks at the transistor gate length versus node, and perhaps the metal 1 pitch. Chip companies are taking different approaches to their advanced node development, regardless of whether the focus is on raw performance, power consumption or, of course, price. To take a specific recent case, Matsushita’s latest 45 nm device has gate lengths similar to some 90 nm devices – so to evaluate on this alone would certainly be misleading.

In point of fact, if we look at the data there is very poor correlation between the node and the implemented features (Figure 1). The closest predictor of the node is the contacted gate pitch – perhaps this can be the node marker?

Figure 1: Measured lithographic features vs.. Technology Node (source - Chipworks reports)

If the correlation is not in specific feature dimensions, then the obvious marker could be ubiquitous circuitry. The benchmark cells for SRAM and NAND flash seem to be quite robust markers for the technology node (Figure 2). Again, using the 45 nm node as an example, Matsushita’s first 45 nm part has SRAM cell sizes as small or smaller, than Intel’s first 45 nm part. And the layout of the cells is what drives the functional density. With all devices tracking similarly, how do you know where you stand?

If you aren’t differentiating on feature size then you need to differentiate on performance and measuring the transistor is no longer the only suitable method. Intel knows this and at 45 nm has been quoting shift register frequency as measurable proof of their performance advantage over previous node devices. We know that racing to the smallest feature sizes can deliver many different advantages depending on the strategy you are employing. In promoting your success, it seems that today, proving the performance means a lot more than proving the size. It really is how you swing the axe, and not just its size; or in the case of advanced CMOS technology, lack thereof.

Figure 2: Technology nodes for SRAM and NAND Flash (source: Chipworks reports)

This look back at history shows that the notion of a “node” is no longer really important. The memory market went off the rails a while back and has pretty much done its own thing. The rest of the logic market appears to be on the same track. More than ever, those competing at advanced nodes, promote features targeted to the application, rather than a leaps-and-bounds approach to smaller-faster-better.

Memory cell predictability does not tell the whole story as companies are adopting a wide variety of different strain engineering, gate materials and metal and dielectric stacks. These design choices are being made to optimize chips to specific applications and cost requirements. Therefore, benchmarking R&D requires an understanding of multiple devices to adequately benchmark your own processes. Since 45 nm is still very new, with many expected design innovations, lets look at what’s coming from the leading manufacturers and, of course, what will find its way into Chipworks' reverse engineering labs:

AMD
Partnership with IBM. Likely foundries IBM East Fishkill, AMD Dresden (Fab38?) (quad core samples from Fab36). 300 mm wafers expected to be commercially available second half 2008 (could be 2009).

Chartered
Likely licensing IBM technology.

Fujitsu
Showed NiSi FUSI gate, stress memorization at 2007 IEDM. Company roadmap shows 2008 release.

IBM
Have announced metal gates, hi-k gate dielectric. Expect production mid 2008 at East Fishkill fab.

Infineon
Partnership with IBM, Chartered, and Samsung. Initial chips fabbed by IBM. IBM, Chartered and Samsung expect to be qualified end 2007. No time table for Infineon.

Intel
In production: metal gates, Hi-k gate dielectric, SiGe.

Matsushita
In production. Die shrink from 65 nm?

NXP
Likely 2008. In partnership with TSMC. RF-CMOS most likely from TSMC.

SMIC
Has licensed IBM’s 45 nm bulk Si process (announcement Dec 2007).

Sony
Expected to announce 45 nm at 2008 ISSCC conference. Expected to be in PS3 game machines.

Sony has sold foundries to Toshiba, so PS3 chip likely to be fabbed (bulk Si) by Toshiba. Cell and RSX graphics chip (?) to be fabbed by IBM on their 45 nm SOI process.

TI
Had started work at DMOS6 fab, but has decided to go with foundry partners. Likely to be using TSMC, UMC, and possibly SMIC.

Toshiba
In partnership with NEC to develop 45 nm process.

TSMC
Qualification finished Sept 2007 (production 2008 for Altera?). Immersion lithography, extremely low-k dielectrics.

Showed gate last metal gate, SiGe, high-k gate dielectrics at 2007 IEDM.

UMC
Demonstrated (Nov 2006), strain engineering? Immersion lithography.

Announced 65 nm RFCMOS process (Oct 2007).

It's All in the Circuitry - DVB-H Goes Mainstream

In late November, DVB-H was ratified in Europe as the mobile TV standard. Already backed by products shipping from big semiconductor companies and cell phone manufacturers, this technology holds good promise as the global standard.

Although consumer adoption hasn’t been stellar as yet, mobile TV pundits use phrases like, “the battle for the third screen,” with the understanding that the ideal model for consuming video content is to be able to do it on the TV, on the personal computer, and on a mobile device (and all three have sockets up for grabs).

For those of us who keep their computers and TVs in different rooms, this is indeed good news. I can already imagine the time that I will save by being able to seamlessly continue watching my favorite show while walking from the office to the family room. Of course, I am being trite, but in my personal life, I am a market laggard when it comes to mobile devices in general.

For the rest of the market, western-based studies have shown that the majority of mobile TV users are kids younger than 24. And what we learned from text messaging is that, if you get them young, then they are yours for life. As an aside, this same study has found that the main time that people watch mobile TV is in bed at night. I can’t help but wonder what they are watching.

So, the market for mobile TV is ripening and the competition for the key sockets is intense. There are many different approaches to designing devices for this market, including single-band solutions designed to minimize power and footprint, and multi-band options that can decode multiple standards. In either case, they need to be able to decode signals quickly, in noisy environments, and with decent quality. At the same time, competition in this market segment forces designers to do so at the lowest possible cost. With billions of cell phones out there begging to be upgraded, we thought it a good time to look at some key features of a leading multi-band device.

The majority of the innovation in these devices is in the architectural and high-level design decisions made by the design team. As per all designs, making the right decisions at this early stage of the process, makes the greatest impact on the final product. The device we will look at is the MaxLinear MxL5005 multi-band tuner, a small device that packs a lot of features (and TV tuner standards) onto a single chip.

MaxLinear has built an integrated tuner IC, capable of receiving and decoding DVB-H, DVB-T, ISDB-T, ATSC, NTSC, SECAM, and PAL. To allow for this, the MxL5005 has a huge tuning range of 44 to 885 MHz.

The MaxLinear MxL5005 global Standards Silicon IC Tuner annotated die photo, with the DC offset cancellation subsystem highlighted in yellow. For more details, or for a higher resolution image, please contact us.

The MxL5005 uses an innovative architecture which receives RF, down-converts to a fixed frequency (probably baseband in fact), then is mixed to a programmable intermediate frequency (IF). This is an unusual design compared to other modern tuners (i.e. the Freescale PC44CD02 DVB-H tuner) that use only a single direct conversion (RF to baseband), or an RF to IF to baseband architecture. The MxL5005 IF is programmable, and can be mixed to anywhere from low-IF to 57 MHz. Presumably, this multi-standard chip requires the IF stage to handle the multitude of standards and demodulator requirements. Other possible advantages include:

• More precise signal filtering can be done at a fixed baseband or low-IF frequency than can be done at the programmable IF stage
• Signal is up-converted to IF range, to allow for an off-chip IF demodulator
• MaxLinear’s designers wanted to patent this, or to avoid patent infringement

The fixed frequency baseband circuitry is a fascinating block on this chip. Here we see relatively simple low pass filters being used to perform channel filtering. This is doubly impressive when you consider that this chip requires no external SAW filters for digital applications. MaxLinear uses dedicated on-chip circuitry for filter auto-calibration, consuming a large percentage of the die. Due to the large gains required in this block, the DC offset becomes a problem and needs to be corrected. MaxLinear performs this correction in a unique and sophisticated way – the MxL5005 employs a large DC offset cancellation subsystem, which also occupies a significant area of the die.

Despite using all of the above-mentioned additional circuits, the MxL5005 die is still very small, and the device is attracting a lot of attention as a truly innovative part.

Terry Ludlow, CEO Chipworks

Recently, I wrote an article called "Culture Trap - Why Japan Is Still Waiting for Its IP Revolution" that was published in the December issue of Intellectual Asset Magazine (IAM). An excerpt from the article published on IAM’s blog sparked several comments, including one from Christopher Morgan, a Japan-based IP manager with Toyota, who questioned the premise of the piece. I felt Mr. Morgan’s comments were worth addressing, both on the IAM blog and here for our readers. Before reading the blog below, however, I invite you to review the full article which is posted at www.Chipworks.com

Christopher Morgan is absolutely right when he writes, “IP is probably one of the most significant issues in Japan for all companies.” He is also correct in saying that innovation is at the heart of the Japanese business culture. The point is, however, the majority of Japanese businesses do not execute effectively on their programs to protect and capitalize on the value of their IP. Japanese companies within the semiconductor and microelectronics industry own more than half of all patents issued worldwide in the field, yet they continue to pay licensing royalties to companies who are less Innovative and have much weaker IP portfolios.

In my article, I do not advocate a litigious approach as the only method of protecting and extending the value of IP. However, litigation is an important, most probably an essential, tool in enforcing IP rights. Japanese companies compete in international markets. Their culture of agreement, consensus, and balance works in many aspects of business, and can be very effectively leveraged in an IP discussion with the threat or fact of litigation as a component of the balance. Japanese companies within the semiconductor and microelectronics business have not built effective patent assertion programs into their IP strategies, in support of their business strategies. As a result, Japanese companies that generate massive amounts of innovation and patents are continuing to pay significant licensing fees to competitors who disproportionately benefit. The paucity of resources devoted to supporting licensing negotiations reflects the lack of understanding that these Japanese firms have about the value of their own IP, and the smorgasbord of tactics that could be used to leverage the significant value in them.

Only IP strategies and tactics that mesh with corporate, business, and cultural mores will be effective. I do, however, believe that Japanese companies have missed enormous opportunities, by not developing IP strategies as effectively as they do sales or marketing strategies, as part of their business plans. I also believe that without a strong IP strategy, Japanese companies will continue to miss out on potential sources of lucrative revenue. In my opinion, it’s time that these companies, in their own manner but as effectively as their Western counterparts, start making the competition pay to play with their hard earned IP.

I am sure many of you have strong opinions on strategies Japanese companies employ around their IP. I would be delighted to hear them, and to continue this discussion here on our blog.

The International Solid State Circuits Conference (ISSCC) is coming-up and Chipworks has decided to host a suite to show off its latest tool for interactively navigating the results of circuit reverse engineering - the ICWorks Browser. With this, one of our engineers muses on what topics he is looking forward to.

  - Randy Torrance

OK, I’m an engineer, and I don’t get out much, but I can tell you that I am really looking forward to this year's ISSCC event.

Once again this year, the premier world-wide circuit conference has some good looking papers. The excitement for me all starts on Sunday evening with the “Special Topic Session” on Green Electronics. You know Green is the topic of the day when it  makes it as a session at a circuit design conference. I am looking forward to seeing how the different sectors of our global electronics industry are trying to be more environmentally conscious. It certainly isn’t easy in an industry like ours.

Also on Sunday evening is another interesting looking session: MEMS for Frequency Synthesis and Wireless RF Communications (or life without quartz crystals). Yes, another opportunity to integrate yet another component on a chip. It seems that eventually every product is going to be run on one chip, but for now we can continue to expect board shrinkage. The MEMS area has been exploding for the last couple of years, and we’ve done a lot of work on this here at Chipworks. It's interesting to see that MEMS seems to have now made the big time. SiTime’s paper on Silicon Resonators for Ultra-Compact, High-Performance Timing References is definitely on my dance card.  

The formal opening of the conference is on Monday morning, with a selection of plenary sessions. These do look like a mixed bag, but I think most people will be interested to see what Mr. Hyung Kyu Lim, CEO of Samsung’s Advanced Institute of Technology, thinks is coming in the "2^nd wave of digital consumer products." This semiconductor and electronics behemoth is obviously going to be a key player in whatever waves are coming. What is my digital home going to look like 10 years from now? Also on Monday morning, "have you ever wondered why a computer can’t be more like a brain?" It looks like Jeff Hawkins of Numenta will answer that question for us.

Monday afternoon the technical sessions commence. The first session is on Image Sensors and Technology. While Chipworks is on the pulse of what is hot (i.e. shipping) in terms of circuits, processes, and systems in this market, it is nice to look ahead at events like this. Many of the ISSCC papers look to be going well beyond the state of the art on the market today. At the extreme of sensitivity, is a single-photon sensor from EPFL and a 140dB dynamic range CMOS Image Sensor from Matsushita. At the extreme of size, is a chip from Stanford University with 0.7µm pixels. Also, some of the big players in this industry are unveiling new designs, including Micron, Kodak, Dalsa, and Toshiba. With 10 papers crowding this session, it will be busy.

Monday evening also has some interesting and less heavy sessions. For me, I think I’ll have to drop in on the Private Equity discussion. These financial firms have been snapping up technology companies lately. Is this a good thing? Also, as a Canadian, I really need to drop by to see what my former Prime Minister has to say about it (Paul Martin is on the panel).

At the end of the Tuesday afternoon sessions, Chipworks is hosting a reception suite. With all these technical sessions my brain will probably be mushy and it will be nice to take a short break and have a glass of wine. But not too much, because after the demonstration I will be back in the conference.

Once again this year, the Microprocessors session promises to be a standing room only affair. The usual suspects are there, including two papers from Intel, two from Sun, and one each from IBM, Renesas, and Tilera. Intel will be describing their 2-billion transistor, 65nm Itanium design. This 700mm² monster has four dual-threaded cores that can communicate with each other at the astounding rate of 96GB/sec. Get there early.

On the wireless front, Ultra Wideband(UWB) is obviously getting closer and closer to reality. This year there are nine papers in this session, and they cover the gamut from transceivers to frequency synthesizers to cameras (yes, cameras!). There is also a session on mm-wave technology, with operation as high as 95GHz.

And finally, the latest boogey-man of deep sub-micron design is process variation. This issue is very hot for Chipworks' customers, so I hope to learn some new things in a nine-paper session on Wednesday morning, combined with a Thursday forum on this topic. Hopefully, they’ve found some good solutions.

I look forward to bringing back all the great new information and reporting on these innovations in future blogs.

The Wheel Turns Full Circle - Hypothesizing on Intel's process at 45 nm.

Written as stand-alone review of Intel's 45 nm published research and announcements, this blog entry can be considered part 3 of "The Path from Pentium to Penryn". While full analysis of the Penryn device is underway in our labs, there is no recipe book for getting inside a 45 nm device. We expect multiple metal types, metal gates, and layers that are as thin as 1 nm. Therefore, while we wait for the results, let's look at what we expect to find.

Dick James, Senior Technology Analyst
Gary Tomkins, VP Technical Intelligence

Intel has been teasing us again for the last couple of years with pre-announcements of the 45-nm process, leaking out (deliberately) imprecise information. From these, we can conclude that they will be using a hafnium-based high-k gate dielectric with metal gate electrodes. Gordon Moore has blessed the news by marking it as the biggest change in transistor technology since the introduction of polysilicon gates in the late '60s.

History really does have a way of repeating itself in the semiconductor industry. Back in 1973, 8 of the leading 10 MOS suppliers (illustrious companies such as Mostek, AMS, AMI, GI , Signetics, along with TI) were producing all or most of their MOS parts with Aluminum-gate PMOS. Intel was the lead company going away from metal and producing all of their MOS devices with silicon gate NMOS and PMOS [1]. All of this is a trip down memory lane for me (DJ), since I started with Philips in 1971 making their equivalent of Intel's 1186 1-kbit poly-gate PMOS DRAMs (using 10-µm design rules!). Fast forward to today and Intel leads the technology push with metal gate MOS. What comes around truly comes around in semiconductors.

In November 2003 Intel made a splash with the announcement that they had identified the elements of high-k/metal gate transistors, and that they were targeting them for their 45-nm process to be launched in 2007 [2]. The paper described the use of atomic layer deposition (ALD) to grow the high-k gate dielectric; then they went into quiet mode for almost three years.

In January '06 they showed off the first 45-nm SRAMs, with a 0.346 µm2 cell size. The big announcement of high-k/metal gate came a year later.

At the end of January 2007, Intel proudly showed off the world's first working 45-nm CPU, made with a high-k/metal gate process. The claimed technology benefits were ~30% reduction in switching power, >20% improvement in switching speed/>5x reduction in S/D leakage, and >10x reduction in gate dielectric leakage. They also predicted production in the second half of this year - and with the evidence in Chipworks labs, they are delivering on this prediction.

Not much leaked out since then, until the IEDM 2007 press tip-sheet announced that the process includes "1-nm electrically-thick high-k dielectrics; dual-band-edge work function metal gates; trench-contact-based local routing; third-generation strained silicon; nine layers of copper interconnect with a low-k interlayer dielectric; low-cost 193-nm dry patterning for critical layers, and lead-free packaging." Interestingly, Intel is one of the few companies said to be employing a dry patterning technique at this node.

Which does not say much more, really, except that at 9.30 am on Tuesday 11 December, all will be revealed by Kaizad Mistry and 49 other authors [3] (et al. really means something at Intel!).

Actually, the 50 authors of the IEDM paper speaks to the complexity of getting a high-k/metal gate process into production. For a literate description of the challenges and process the Intel team have gone through in the last few years, see the article in the October issue of IEEE Spectrum [4].

Summarizing what we know:

• Hafnium-based high-k dielectric, 1 nm equivalent oxide thickness (EOT), ALD used
• Different metals for NMOS and PMOS gates (not FuSi)
• Gate-last process to form gates
• Strained silicon is still being used
  

(source = Intel)

Figure 1 shows Intel's image of their high-k gate stack from the January announcement. Conveniently, it is a high-resolution TEM image, and we can see the (111) crystal planes (assuming the normal <110> channel direction), which allows us to calibrate it, since the (111) spacing is 3.13 Å. I have placed a calibrated image on the right, and at least in this sample, it appears that the high-k layer is ~2.3 nm thick, and the metal ~5.8 nm thick. So if Intel's process uses EOT 1 nm, the k-value of the new dielectric is ~9.0, since SiO2 has a k of ~3.9.

When it comes to the gate metals, so many variations have been tried that it is almost impossible to make a prediction as to what Intel are using. Just looking at the work functions across the periodic table is no help, since high-k dielectrics (and their methods of formation) alter the work functions, so it really does become a shell game. No wonder it's taken years to get to this point!

For a hint, we looked into Intel's patents on metal gates, and they filed a whole bunch at the end of 2003, just after the press announcement. The claims are of course imprecise - it is the job of a good patent lawyer to disclose the invention while giving away as little detail as possible. Scanning through the claims gives us the following:

• High-k dielectric - HfO2, HfSiO
• " NMOS - Zr, W, Ta, Hf, Ti, Al, Metal carbide, transition metal aluminides (e.g. Ti3Al, ZrAl)
• " PMOS - Ru, Pa , Pt, Co, Ni, TiAlN, WCN, Metal oxide
• " Low resistance layers - TiN, W, Ti, Al, Ta, TaN, Co, Ni

We can rule out HfO2 for the dielectric since the k-value is too high (25 - 30); since SiO2's k~3.9, presumably the k can be tuned by adjusting the amounts of silicon and oxygen in the layer, either during the ALD process or by subsequent processing. Also, judging by the literature, HfSiON seems to be the consensus dielectric material, with a nominal k of ~12, which can be also tuned by ozonization or nitridation. These patents were filed 3 - 4 years ago, so it doesn't seem to be an unreasonable to suppose that a silicon-rich HfSiO or HfSiON layer could be used here.

A clue may be that the gate leakage reduction is quoted as >10x, whereas HfSiON references typically quote >100x reduction in leakage [5]; higher Si content would presumably increase the tunneling capability of the dielectric. Most high-k references also discuss using an interfacial monolayer with a high oxygen content, to maintain carrier mobility; this would also reduce the effective k-value.

When it comes to the metals, we should be able to rule out aluminum because of the subsequent thermal processing, but that still leaves us quite a few alternatives. The use of carbides, aluminides, and oxides is an interesting reflection of the variety of different materials investigated by Intel.

Figure 2 shows the gate-last structure from US patent 7,157,378 which agrees with the layer structure in Figure 8. Features 115 and 119 are the high-k dielectric, 116 and 120 are the work function metals, and 121 and 118 are the low resistance layers. The remaining features 101 and 102 are the substrate wells, 103 the isolation, and 112 a dielectric layer.
This structure requires complex processing; creating a conventional transistor structure, and then replacing the sacrificial gate with metal gates.

I will pass on trying to make an educated guess at the work-function metals, since I have no information on the interaction of the multiple candidates with the possible dielectrics - those of you in the fabs working in the technology will have a much better idea!

Of the possible low-resistance filler metals, tungsten, tantalum, and titanium and tantalum nitride are the ones that appeal, simply because the CMP of them is already well established in manufacturing. Of course, there may also be interactions with the work-function metals that limit the field, so again it is difficult to make a solid prediction.

So, apart from the ground-breaking materials technology, with all the extra fabrication steps indicated above, Intel has also introduced a whole new level of process complexity.

We'll find out as we get inside this exciting technology!

References

[1] Chipworks (ICE) “Status 73” The Integrated Circuit Industry

[2] R.Chau et al., “Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-K” International Workshop on Gate Insulator, pp. 124-126, November 2003.

[3] K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”,International Electron Devices Meeting Technical Digest, paper 10.2, 2007.

[4] M. Bohr et al., “The High-k Solution’, IEEE Spectrum, pp. 29-35, October 2007.

[5] M.a. Quevedo-Lopez et al., “High Performance Gate first HfSiON Dielectric Satisfying 45nm Node Requirements”,International Electron Devices Meeting Technical Digest, pp. 437-440, 2005.

The Path from Pentium to Penryn - Part 2

Things start to literally heat-up as we move to smaller transistors and a more sophisticated BEOL for the time. With the Intel 45 nm Penryn device that Chipworks is currently reverse-engineering, we will see even further innovation at the transistor level. This 2-part retrospective takes you through Intel's history of transistor innovation, in preparation for shipment of the latest reports on the Intel 45 nm Penryn processor.

Ray Fontaine, Process Analysis Engineer

Late in 1999 we saw the Intel 650 MHz Pentium III “Coppermine” processor built using….Al. Rather than making multiple changes at the same time for this node, Intel first produced parts with scaled transistors using an Al backend. Later on they would migrate the backend to Cu and further tune the transistors. The Coppermine part we saw in 1999 had 0.08 µm gate length NMOS and 0.10 µm gate length PMOS transistors. The gate sidewall had a “notched” profile being slightly narrower just above the channel to reduce the physical gate length. And perhaps the most significant change was the adoption of Co silicide on the gate electrodes and S/D diffusions. The part had six levels of Al metal, a metal 1 pitch of 0.50 µm and an SRAM cell size of 2.2 µm x 2.6 µm (5.7 µm²).

We saw the 1.5 GHz Pentium 4 “Willamette” processor introduction in early 2001. It was made using a 0.13 µm Al CMOS process. It had a similar transistor structure as the Coppermine part, had 0.09 µm gate length transistors, a metal 1 pitch of 0.47 µm and an SRAM cell scaled down to 2.1 µm x 2.3 µm (4.8 µm²).

1999 – Intel 650 MHz Pentium III “Coppermine” Processor (0.08 µm gate length)

We saw the first Cu part from Intel in 2001 in a 1.2 GHz Pentium III Processor featuring 44 million transistors. The Cu backend aside (it was a major achievement), the gates now used a buffer oxide and an L-shaped silicon nitride SWS. The minimum gate length was 0.07 µm for NMOS and PMOS transistors. The minimum metal 1 pitch was 0.47 µm while the SRAM cell size was down to 1.7 µm x 2.0 µm (3.9 µm²).

2001 – Intel 1.2 GHz “All Copper” Pentium III Processor (0.07 µm gate length)

2004 was a big year for Intel’s ever shrinking transistor. The 2.8 GHz “Prescott” Pentium 4 processor implemented transistor strain – tensile nitride strain applied to the NMOS gates and an embedded SiGe S/D to apply compressive strain to the PMOS channels. The gates used a buffer oxide and a thin silicon nitride SWS. They weren’t done with the materials changes either; Ni silicide was brought in for the gates and S/D diffusions. The minimum gate lengths observed were 45 nm for NMOS and 60 nm for PMOS. Seven levels of Cu were used with a minimum metal 1 pitch of 0.23 µm and a 6T SRAM size of 0.90 µm x 1.35 µm (1.20 µm²).

2004 – Intel 2.8 GHz “Prescott” Pentium 4 Processor (0.045 µm gate length)

2006 saw the evolution of the 90 nm process to a 65 nm process with a lot of tweaks to the transistors. The 2.8 GHz D920 “Presler” dual core processor featured nominally 42 nm gate length NMOS devices and 38 nm gate length PMOS devices. Of course line edge roughness at these geometries contributes to varying gate lengths, but gate length scaling continues albeit at a slower pace. The part used a simplified sidewall structure and we noticed that the silicide for PMOS devices contributed to most of the gate electrode thickness (in a way, a preview of coming attractions). The part used eight levels of Cu, had a minimum metal 1 pitch of 0.21 µm and featured an SRAM cell size of 0.48 µm x 1.30 µm (0.62 µm²).

2006 – Intel 2.8 GHz D920 “Presler” Dual Core Processor (0.038 µm gate length)

So now the market waits for Intel to raise the curtain on their 800-million transistor 45 nm Penryn processors, while we at Chipworks go inside the devices that we already have in our labs. Much has been written on the subject, but the IEDM 2007 tip sheet offers a nice summary[6]: “Highlights include 1-nm electrically-thick high-k dielectrics; dual-band edge-work- function metal gates; trench-contact-based local routing; third-generation strained silicon; nine layers of copper interconnect with a low-k interlayer dielectric; low-cost 193-nm dry patterning for critical layers, and lead-free packaging. Intel has used the process to manufacture a 153-Mb SRAM memory array with an SRAM cell size of 0.346µm², as well as multiple microprocessors”.

Looking ahead, we’ll be showing you the smallest SRAM cell (expected at 0.346 µm² ) amongst many other things. Following the trend line (below), we should expect a minimum physical gate length no shorter than about 30 nm. Contact us for a white paper from our very own Dick James on his research into Intel’s 45 nm technology; or to order our coming process report and transistor characterization. And coming soon, more on packaging and process flow analysis.

Intel ‘Penryn’ Family Microprocessor - order your report from Chipworks

Gordon Moore has been widely quoted as saying “The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s”.

We’ve seen the evolutionary nature of MOS transistor design, but perhaps more impressive is Intel’s aggressive pace in process development. The amount of innovations we see per node seems to be increasing exponentially. But then again, Intel invented Moore’s Law, and they’ve stuck to it so far.

The Path from Pentium to Penryn

Intel Transistor Innovation - Part 1

Chipworks is releasing a special 2-part blog covering Intel's transistor design history in celebration of the fact that we now have the Penryn processors in our reverse engineering labs. Part 2 will be published on October 22nd with even more advanced research on the Penryn device coming soon thereafter. For more information about our process reports on the Intel 45 nm device please visit our Intel 45 nm spotlight.

Ray Fontaine, Process Analysis Engineer

On November 4, 2003, Intel announced a fundamental breakthrough in CMOS transistor fabrication by implementing high-k gate dielectrics and metal gate electrodes [1]. Moving forward 2+ years, on January 25, 2006 they demonstrated fully functional 6T SRAM test chips manufactured in a 45 nm logic process [2].

Today we are less than a month away from the heralded release of the Penryn family of 45 nm microprocessors. With these parts in our hands, we thought it would be a good time to dust off some of our old reports and put things in perspective by looking at the progression of Intel’s process technology.

Talking about such things in the context of a timeline is nothing new; Intel celebrated the 60^th anniversary of the modern transistor with a nice roadmap of their processor launches [3]. The October 2007 edition of IEEE Spectrum also has a nice write-up by Mark Bohr, et al., on the odyssey of high-k gate dielectric and metal gate development [4]. Without going too far back into the archives, I’d like to parallel these timelines with our own findings.

As a preamble to the Pentium, it’s worth noting that it too was just the next stop in the evolution of MOS transistor design. In Q3 of 1992 we looked at an Intel 80386SX-16 microprocessor and found it to use W silicided MOS gates. The minimum physical gate length was 1.1 µm and the minimum metal 1 pitch was 3.3 µm.

1992 Intel 80386SX-16 Microprocessor (1.1 µm gate length)

In 1993 Intel launched the Pentium® Processor which used 3 million transistors and was made using a 0.8 µm BiCMOS process (The first few generations of Pentium processors also used bipolar transistors). We found 0.65 µm gate length MOS transistors and a minimum metal 1 pitch of 1.9 µm. The MOS transistors used a Ti silicide on the gates and S/D diffusions and employed a simple silicon nitride SWS structure. The part used 3 levels of Al metal and featured 6T SRAM with a 9.3 µm x 12.0 µm (112 µm²) cell size. Note the re-flowed pre-metal dielectric (PMD).

1993 – Intel Pentium Processor (0.65 µm MOS gate length)

1994 brought an Intel P54C Pentium Processor to our doorstep. This one was built using a 0.60 µm BiCMOS process featuring 0.45 µm gate length MOS transistors and a metal 1 pitch of 1.45 µm. The materials used for the transistors remained unchanged. This part used 4 levels of Al metal and featured a 6T SRAM size of 6.0 µm x 7.0 µm (42 µm²).

1994 – Intel P54C Pentium Processor (0.45 µm MOS gate length)

In 1996 we looked at a Pentium Pro microprocessor made using a 0.35 µm BiCMOS process. We found 0.30 µm gate length MOS transistors and a minimum metal 1 pitch of 0.95 µm. The transistors used a Ti silicide on the gates and S/D diffusions and continued to use a simple silicon nitride SWS structure. The part used 4 levels of Al metal and featured 6T SRAM with a 5.85 x 8.45 (49 µm²) cell size. By this time Intel had moved to a full chemical mechanical polish (CMP) process for planarization of the dielectrics.

1996 – Intel 200 MHz Pentium Pro Processor (0.35 µm gate length)

In 1997 we looked at a 200 MHz Pentium Processor with MMX technology. By then the Pentium had gone to a straight CMOS process. We found 0.30 µm minimum gate length MOS, although the Wikipedia entry for the MMX part indicates a migration to a 0.28 µm process [5]. Regardless, the SRAM cell size was shrunk to 4.2 µm x 4.6 µm (19 µm²).

We did see the 0.28 µm CMOS process in 1997 in a 266 MHz 32-bit Pentium II (Klamath) processor. The parts featured minimum MOS gate lengths of 0.25 µm and a minimum metal 1 pitch of 0.95 µm. The 6T SRAM cell size was 4.1 µm x 4.8 µm (19.7 µm²). The part continued to use 4 levels of Al metal and again no materials changes were made to the transistor gates.

1997 – Intel 266 MHz 32-bit Pentium II (Klamath) Processor (0.25 µm gate length)

In 1998 we saw a 333 MHz 32-bit Pentium II (Deschutes) processor made using a 0.25 µm CMOS process. The part featured 0.20 µm minimum gate length MOS transistors and a metal 1 pitch of 0.65 µm. A fifth level of Al interconnect was added, but again the gate structure remained the same. The 6T SRAM cell size was scaled to 3.0 µm x 4.2 µm (12.6 µm²).

1998 – Intel 333 MHz 32-bit Pentium II (Deschutes) Processor (0.20 µm gate length)

So, with all due respect to the process engineers of the day, the rate of change was fairly slow compared to recent times. I guess you could say all of the low hanging fruit was picked long ago. Anyway in Q2 of 1999 we looked at the 550 MHz 32-bit Pentium III processor made using a 0.18 µm CMOS process featuring 0.13 µm minimum gate length MOS transistors and a minimum metal 1 pitch of 0.70 µm. These parts featured 9.5 million transistors, five levels of Al interconnect and a 6T SRAM cell size of 2.9 µm x 4.1 µm (11.9 µm²). Ok, so still there are minimal materials changes, but hold on things are about to take off.

1999 – Intel 550 MHz 32-bit Pentium III Processor (0.13 µm gate length)

Part 2 coming on October 22nd. Add Chipworks to your RSS feed today.

Ramtron’s latest leaps forward from the prior generation FRAM devices

Rajesh Krishnamurthy

Back in March Ramtron issued a joint press release with Texas Instruments, announcing that TI would be manufacturing a new 4-Mb FRAM using their 130-nm process. This is a notable advance on their previous 1-Mb product, manufactured by Fujitsu in their 350-nm line.

FRAM (ferroelectric random access memory) has access times similar to SRAM and non-volatility better than NAND Flash. It has historically been targeted at lower volume sockets where “hardened” data is required, such as military and industrial applications.

The latest R&D by Ramtron and Texas Instruments delivers an FRAM product that (for consumer electronics) is now positioned in the marketplace somewhere between the above two entrenched memory technologies. Obviously the density may never be at the point where FRAM could replace NAND Flash, nor is the price-point an automatic replacement for SRAM. However, the latest process delivers a dramatic 10-fold shrink over the prior generation (from 8.8 to 0.71 µm²) and when combined with larger-volume sockets we should see the needed cost efficiencies. Because access and cycle times compare very favorably with SRAM and with no requirement for a power source to maintain the state, SRAM sockets will be the volume wins for FRAM technology.

Die Markings

In fact, according to their product release, the FM22L16 is “Pin-compatible with asynchronous static RAM (SRAM), (and) targets industrial control systems such as robotics, network and data storage applications, multi-function printers, auto navigation systems and a host of other SRAM-based system designs.”

Ramtron is heavily invested in FRAM with 91% of their revenue coming from FRAM, up from 35% in 2004. Combine this leadership role with a well-oiled partnership with Texas Instruments and we have a great process for Chipworks to take you inside of in a report on the FM22L16-55-TG 4 Mbit FRAM. Our analysis has already uncovered a few interesting facts.

A Brief History of Ferroelectric Memory Design

Ramtron has provided a overview of the chemical properties of a ferroelectric crystal on their web site. To summarize, an atom in the crystal lattice moves in the direction of the applied electric field. Once that field is removed, the atom stays in place. This type of technology has been shown to be much more stable than NAND Flash memory, which is known to have a limited (albeit long) re-write capacity.

Ramtron claims only two extra mask steps are needed; “The 0.4u² capacitors are patterned using a single mask, and a second mask makes the connection between the top electrode of the capacitor and metal. The two-mask adder compares very favorably with the 5-7 masks required by other memory technologies and makes FRAM an ideal solution for embedded nonvolatile memory. The FRAM process insert has almost no impact on the underlying CMOS technology, thereby allowing full use of TI’s rich standard cell library. Ramtron has already developed follow-on products that are currently under test.”

Ramtron's conceptual drawing of their FRAM structure

A typical capacitor places a ferroelectric crystal lattice between 2 electrodes (the red line in the image above). This arrangement, combined with the properties of programming the cell mean that write times are extremely fast while power consumption is much lower than floating gate cells. Additionally, improvements in the process have allowed Ramtron to use the 1T/1C transistor arrangement without the need for a complement cell for reference.

FRAM Capacitor

Looking very closely at the ferroelectric cell we can see the grains of the lead zirconate tinitrate (PZT) sandwiched between the capacitor plates. The PZT has tetragonal unit cell closely matched to the lattice constraints of the electrodes to allow the growth of a strain-free layer. The process is optimized with a different top electrode material in layer 1 to compensate for the lumpiness of the PZT crystals.

High Magnification of Electrodes and PZT

TI Fabricates the device….or do they?

Another interesting thing about this device is that the transistors in this part do not use the differential oxide spacers. We can conclude that either TI is doing something unique for Ramtron or, to save costs, the front-end is being farmed out to a low-cost foundry. With the goal of winning higher-volume sockets we assume that Ramtron would be taking the lowest cost approach that delivers the performance they need.

CMOS Transistor in FM22L16-55-TG

FRAM is certainly an interesting technology competing in the highly competitive “emerging” memories space that includes MRAM, FRAM, FeRAM, PRAM and PCRAM. The process technologies and strategies that these two leaders employ have delivered a product with impressive specifications and even more impressive fabrication.

Comparing the SMB380, SMB365 and SMB363 Accelerometers

contributed by St.J. Dixon-Warren

Back in June we blogged about the reduction in die size of STMicroelectronics LIS3L02AE and LIS302DL as they transited from analog to digital design. Now we have seen the same trend in another leading edge MEMS manufacturer, Bosch Sensortec (the consumer spin-off of Bosch’s automotive MEMS division).

According to Bosch Sensortec’s product flyer, the SMB380 is a low-g acceleration sensor with a digital output, targeted at the consumer electronics market. Suggested applications include hard disk protection, pedometers and gaming. It comes packaged in exceptionally small package, 3 mm x 3mm x 0.9 mm thick. The current consumption is 200 µA with V_DD = 2.4-3.6 V.

SMB380 Package

Decapsulation of the SMB380 reveals a hermetically sealed MEMS device connected by ten wire bonds side-by-side with an ASIC die. The hermetic lid covers most of the underlying MEMS die and notably does not feature a bonding wire connecting the lid to the MEMS die. The ground wire is typically required to create a Faraday Cage around the MEMS device, so to us this implies the use of a conductive epoxy to seal the device rather than the usual lead-doped glass.

Decapsulated SMB380 ASIC and MEMS Dice

Removal of the cap die reveals the internal structure of the MEMS acceleration sensor, which Chipworks has compared to the MEMS sensors found in the SMB363 and SMB365.

As we noted above, the SMB380 uses a 3 mm x 3 mm x 0.9 mm QFN package. By contrast, the analog SMB363 and the digital SMB365 both use the CMB365 MEMS die packaged in a 4 mm x 4 mm x 1.2 mm QFN package. The CMB380 die is only 2.01 mm x 1.27 mm (2.55 mm²) as compared to the 2.19 mm x 3.03 mm (6.63 mm²) CMB365 die, corresponding to a ~60% shrink in the die area.

SMB365 Die versus SMB380 Die (not to scale)

SMB365 Showing Device Stack

The ASIC for the SMB363 and SMB365 is stacked over the MEMS die, which has a hermetically sealed cap. In contrast, the SMB380 uses a side-by-side arrangement for the MEMS and ASIC dice, which together with the absence of the bonding wire to the lid, allows Bosch to reduce the height of the package by 25% from 1.2 mm to 0.9 mm.

Summary Table

The layout of the CMB380 shows three sensors – for X, Y and Z – arranged linearly on the die, while the CMB365 shows the three sensors arranged within a rectangular area in the central area of the die. The CMB380 sensor occupies at 0.33 mm x 1.43 mm area (0.47 mm²), while the CMB365 sensor occupies a 1.70 mm x 1.16 mm (1.35 mm²), corresponding to 18% and 20% of the die area respectively.

Bosch's decision to spin-out a division dedicated in-part, to consumer electronics applications appears to have paid off with a device that shows innovation over the prior generation of accelerometers from Bosch. Mathieu Potin from Yole Developpement (a Chipworks partner), has pointed out that although the growth forecast for accelerometers is very robust at 31%, price competition has also been fierce. With players like Bosch responding on both price concessions and innovation, the pressure is on for new entrants to make a profit..

Chipworks has commenced a full MEMS Process Review (MPR) analysis of the Bosch SMB380, which will include analysis of the QFN package, the process used to fabricate the MEMS, ASIC and cap dice, and the architecture of the CMB380 sensor.

All Quiet on the Blogging Front – and then there was IDF

Dick James

Things have been a bit quiet lately; not that there haven’t been topics worth commenting, just that work life has been really, really busy for all of us.

That hasn’t changed, but I’ve had a few days in California at the Custom Integrated Circuit Conference (CICC) where Chipworks presented on the state-of-the-art in reverse engineering, and the Intel Developer Forum (IDF), and they sparked a few thoughts.

I’ve never been to IDF before, and it overwhelms with the kind of high-tech hype that Intel, Apple and Microsoft are becoming famous for. Keynote speeches, big stage, lots of lights, fanfares worthy of a mediaeval monarch, as the CEOs come out to make the big announcements – these guys have been watching the Oscars! That’s not a strange parallel – they are paid as much as film stars these days!

Aside from all that, there are a couple of nuggets that came up; the Intel 45-nm parts will be released on November 12, and Intel have actually drawn ahead of their two-year cycle, since they are showing off 32-nm test SRAMs; if I remember rightly, the 45-nm SRAM announcement was in early 2006. So of course we’ll be looking for the 45-nm parts as soon as they’re out there!

Associated with the technical sessions is a Technology Showcase – lots of booths by Intel, but also associated companies big and small, from Microsoft to small focused companies like Siano (mobile TV chips) and Akustica (MEMS microphones).

Intel Research also had a big presence, there was a row of demonstrations showing off leading edge stuff like power management and improving the discrimination of wireless links – not just within the chip and board design, but actively monitoring the environment and compensating for the other activity that is going on. We live in a very noisy electromagnetic atmosphere these days, everything from microwave ovens to Bluetooth links and mobile/portable phones using multiple frequency bands, so it’s not surprising that there’s room for improvement.

The display that really caught my eye was part of their Terascale Computing program. It was a wafer of alternating (65-nm) SRAM and 80-core processor dice, and there was a working demo of the processor running at >1 – 2 teraflops, using 100-200W. It seems the target is to achieve teraflop computing at <100W, and on this evidence Intel has done it.

Figure 2: Future tera-scale chips will use an array of tens to hundreds of cores with reconfigurable caches, as well as special-purpose hardware accelerators (image from Intel Whitepaper)

This is very much still a proof-of-concept exercise – don’t expect to see these on the market any time soon! The 80 cores are dedicated floating-point processors, not Presler-type cores (the die would be huge!), and the exercise is to use these parts to experiment on topics such as data-path routing, power management using multiple cores, and the many other technical concerns there are.

There are some interesting features in the processor already, though; the cores are designed to be operated independently, and the physical routing layout is such that they can be grouped in multiple different ways. Each core has a six-way routing block, including out-of-plane – they are anticipating stacking the die with a memory chip at some point. In fact, the SRAM parts on the demo wafer were laid out to allow for through-silicon vias or face-to-face stacking with the processor die. I had not realized that Intel had been doing so much package development, but apparently their guys in Arizona have all the infrastructure to handle 70-micron-thick dice and stacked packaging – for them, it’s not how to do it, it’s when.

It also seems that each core has in-built temperature sensors, so that if a core gets too hot the power can be managed by lowering voltage or frequency, as is already used in today’s processors, but in this case it also allows core-swapping to switch the processing to another (cooler) core. Just one way of controlling power, since it could also be done by other techniques such as tweaking duty cycles, etc.

Terascale Computing is Intel’s largest R&D program, with ~250 people working on it globally, so definitely something to watch, and a pointer that the processor business is likely to go beyond the eight cores of the Cell processor by an order of magnitude or more. We’re already seeing the trend in specific applications such as graphics processing – the Nvidia G80 has 128 cores, but I gather that they are not usable for more generic applications.

One of the more eerie things about the forum was the RFID tags on our badges; we were tracked from room to room as we wandered around Moscone West. I’ve not been before, so I don’t know if this routine or not. This was used so that we could log on to the survey website for the sessions, and give our opinions – the website automatically listed the sessions attended so that we didn’t have to scroll through the long list of papers. A high-profile use of the RFID location was during the Thursday keynote – there was a draw for concert tickets, and the lucky winner was identified as being in the room, since we were all tracked going in there.

Most of the topics were user-oriented, so software, user environment (Internet, etc), and architecture, so way out my field as a process nerd. The keynotes are available in streaming video on the IDF website, but most of the presentations are passworded for attendees – but for a trip down memory lane watch the video of Gordon Moore, it’s a great reminder of how far the industry has come in the last forty years.

An interesting couple of days!

There are two basic types of R&D. The R&D that keeps you in the game and the R&D that adds competitive differentiated value to your company – something that makes you better than the competition. There is a common strategy in the semiconductor businesses that when the latter ceases to become a differentiator it is time to spin out the business to prepare it for inevitable market consolidation.  Doom and gloom? Definitely not. Investment – innovation – maturity is part of the natural cycle for all R&D intensive industries.

But how do you know where you are?

Causes for the innovation crunch can vary from physical limitations (in the case of image sensors it could be considered the wavelength of visible light) to margin shrinkage (after all, you can’t invest without cash flow). The answer is that savvy business unit managers look at both (and of course, Chipworks helps by focusing on the technical innovations).

Rather than a historical lesson in a mature market like NAND flash, I think it will be more interesting to speculate on one of the latest markets. Let’s use Micron’s image sensor business unit as a great case study by comparing image sensors of the same generation with published data.

You can look at financial data, socket wins, and even sales pipelines but in the volatile semiconductor industry they don’t always paint the picture on their own. In this case, CMOS image sensors continue to be a hot growth sector and Micron has been in the top 3 from a growth and revenue perspective almost from the start. Moreover, there are still new entrants and new sockets. So, from a pure marketing perspective this industry is still deserving of investment. If you can’t use market data, then you can look to the changing pattern of innovation.

Micron has long been perceived as one of the technology leaders in the image sensor space. And now Micron is now rumored to be considering a sale of this unit. If these rumors are true then why consider this move (Micron does not confirm them)?

Well, in CMOS image sensors in handheld devices we are seeing innovation change from a rapid race to a smaller pixel, to one where product lifecycles are lasting longer. Process tweaks within each respective pixel shrink are becoming more commonplace. We’re even seeing a return to a larger pixel for certain applications where smaller is not always better.

Die Photo for MT9E001I12STC

How does this manifest itself by what Chipworks has reported on about Micron? Lets look at the evidence from Micron’s own recent product lines. We’ll start with the MT9E001I12STC 8 Mp CMOS image sensor. This device was one of the very first to market, with a pixel size measuring only 1.75 um (about 3x the wavelength of green light).

The pixel uses a shared architecture where four photosites share one reset, source follower, and row select transistor, yielding a 1.75T effective pixel.  The pixels are laid out in a standard Bayer pattern, although it is interesting to note that the green filters are consistently larger than the respective blue and red filters. To improve the sensitivity, the layout is designed to maximize the fill factor (amount of space available inside the light tube for light transmission), and added an anti-reflective layer over the photocathode.

Pixel at Poly

Micron has promoted the coming launch of its next generation devices with a 1.4 um large pixel. But as innovation appears to be slowing, they are continuing to “tweak” the prior generation to maximize the quality. I use the word “tweak” in quotations, because the changes that we are seeing within a pixel generation are quite dramatic.

Given the cost of this type of R&D at “super small pixels” you have to wonder if this is a signal by the market leader of a move into the “maintenance R&D” mode.

Let’s summarize these expected changes from a look at the published data about what we might find in the Micron device die marked C26A – the latest 1.75 um pixel from Micron that we have just started analyzing.

Die markings on a recent Micron device

We expect to find that the current device has moved to a more symmetrical architecture as it relates to the individual pixels yet still delivers the same or similar fill factor. This is an about-face from the last few years where the industry has used asymmetric pixels to maximize the fill factor.

To enable this they have gone to an optimized process that reduces the height of the pixel stack to increase the aperture size, and they continue to focus on an aluminum interconnect process when many of the competitors have moved to copper.

Oddly, at the very fine line widths, Al seems to achieve lower electrical sheet resistances, as compared to copper. So this same split of Al vs Cu is being observed in NAND flash memories. Al also avoids the need to extra processing steps to remove the silicon nitride metal seal cap layers from over the pixel aperture. This feature is consistent in Micron’s memory business and is likely the result of expertise and infrastructure at the chosen fab than of image sensor specific R&D (note that Micron has a copper DRAM fab as well).

What else needs to be optimized?

The industry first tackled lens formation for cheap and easy improvements. Next came the transistor layout, again relatively cheap and easy. Today we expect to see the process is being optimized, a typically a higher-cost activity. And in the future we expect to see the physical geometry of the transistors changing as consolidation brings cost advantages, such as larger wafers, and benefits the high-cost R&D that remains for increasing the capabilities of the CMOS image sensor.

In summary, this means that more R&D is required for less total advantage, and the gap between the leaders and the followers will narrow to a point where the market may no longer care. The only way to truly know how far ahead you are is to compare competing devices, but that is a subject for another blog.

(Yet) More on the iPhone – How many ARM cores?

Back on July 6, Peter Clarke at EETimes Europe posed a fun question – how many ARM cores are there in the iPhone? Like many people, I’ve been following the multiple iPhone discussions, and his piece “IPhone teardowns fail to answer the 'ARM question'” caught my attention.

The initial assessment was three – an ARM 1176 in the Samsung applications processor, an ARM9 or 7 in the Marvell 88W8686 WLAN chip, and an ARM926 in the Infineon S-Gold2 baseband controller. There is also speculation that the PowerVR MBX 3D graphics processor is in the app’s processor, also licensed from ARM; and the CSR Bluetooth chip likely has an ARM MCU core in there, bringing the total up to five.
A few days ago I was poking around our teardown of the iPhone, and looking at the touchscreen module, with four chips on it:

iPhone touchscreen module

On the right half of the image, the Apple-branded chip is the Broadcom BCM5973A chip, and on the left half is a Philips (NXP) LPC2221. The NXP one caught my eye, since they have a LPC2220, which is a 16/32-bit ARM7TDMI-S CPU-based microcontroller. Part numbers can be deceptive, so we decapsulated the part, and found this:

Die photo of NXP LPC2221

And lo and behold, with this die marking:

LPC2221 die marking

Which solves that particular mystery – we have another ARM core in the iPhone. Of course that leaves the question, if the NXP chip is the touchscreen controller, what is the Broadcom chip?

During their Q2 call a couple of weeks ago, they specifically referred to the part as a touchscreen controller (my italics);

“On the mobile multimedia front, a decline of our traditional portable device end market revenue was more than offset by initial shipments of the new product with new functions into a recently announced hot new cellular handset. As illustrated by numerous publicly available teardowns, the new touch screen controller demonstrates our ability to create innovative devices for our most cutting edge customers.”

Other teardowns refer to it as an I/O controller. If the touchscreen is a capacitive sensor, then that makes sense – a device is needed to translate the variations in capacity and position into digital data suitable for the LPC2221. That actually ties in with the die photo (below), since it is laid out in the sort of regular array we would expect for an I/O part.

The ‘59’ prefix to the part number is a bit confusing, since the only 59*** parts on their website are power management units (BCM59000 series), and I believe those are fabbed by AMIS. This sort of product would be in the AMIS product range, though, so maybe the ‘59’ means “fabbed by AMIS”. Pure speculation, I know..

There certainly does not seem to be any large logic block on it such as an ARM CPU, anyway. And strangely, the copyright date on the chip is 2004, so either Broadcom has been in the iPhone design loop for a long time, or maybe this is an older part re-engineered to suit Apple’s requirements – another way of keeping costs down (iSuppli estimated its cost at $1.15).

Die photo of Broadcom BCM5973A chip

Copyright mark on BCM5973A

So depending on what you mean by “touchscreen controller”, it’s the Broadcom chip, the NXP chip, or looked at as a whole, the entire module – presumably the other two parts control the power environment for the MCU and the I/O chips.

Anyway, getting back to Peter Clarke’s question – the ARM count is up to six, which with the Wolfson audio codec, gives the UK a good chunk of the IP in the iPhone!

Don't forget to click on the thumbnails to bring up the full images!

contributed by Kevin Gibb

Texas Instruments’ new “fab-lite” strategy showed itself in the products that they delivered to market well before they formally disclosed it. From the package markings Chipworks has seen that they farm-out low cost cell phone chips to their foundry partners while retaining the high-margin DSP business in-house.

TI TMS320TCI6488 - Engineering Sample Package Photo with "X" designation (click to enlarge)

Texas Instruments latest digital signal processor, the TI TMS320TCI6488, is one such high-margin device. The latest 65 nm device is designed for base stations as a highly reliable and scalable solution. While TI has used its foundry partners UMC and TSMC for its 65 nm mobile platform, it has kept its high power 65 nm process to itself for the time being. 

Like any node, moving to 65 nm delivers the standard benefits of cost and performance. However, a simple shrink was not all that TI has done with this device. To get the performance improvements, TI has taken a novel approach to BEOL integration.

Like UMC, TSMC and others, TI has abandoned etch stop layers for its metal lines; a common theme for the 65 nm node as compared to the earlier 90 nm nodes, which often employed these etch stop layers.  TI claims to be using an organo-silicate glass with an effective dielectric constant of 2.8, with SiCN metal seal layers for its back-end processing. Low-k carbon doped dielectrics, such as these, often bring manufacturing problems such as delamination and dishing during the metal CMP processing steps. While adhesion to the carbon doped silicon nitride layers is also a bit of a problem. These appear to have been solved with the TMS320TCI6488 using features that should last beyond the 65-nm node.

TI TMS320TCI6488 BEOL (click to enlarge)

What are the benefits of this manufacturing approach? Not surprisingly, cost maybe one factor since the process would suggest  less materials. Additionally, higher yields and better performance are expected due to reduced ‘dishing’ and delamination of the dielectrics. Overall, the process has also been shown to reduce leakage current.

TI has disclosed that it will be transferring 45 nm DSP technology to TSMC and some similarities between this particular device and other TI-TSMC devices at 65 nm suggest that some of this has already occurred. Therefore, we can conclude that the in-house development of this baseband processor may very well give us insights into the future technology roadmap for a number of foundries.

Texas Instruments has certainly been one of the later entrants into the 65 nm game. This device suggests that they have clearly taken the time to do their R&D and to learn from other processes on the market.

Go west young man. Go SEMICON West!

SEMICON West opens its doors next week, and Chipworks will be there.

The SEMICON West show is one of those places where we regularly go to see the latest tools, technologies, and trends in microelectronics design and manufacturing.

This year we’re in the company of more than 1,250 exhibiting companies.

Drop by and say hello. We’re in booth 8153, West Hall, Level 2. It’s worth your trip, because we’ve got plenty to share – the iPhone taken down to the atomic level and an updated look at the history of Strain. You can get up close and personal with the Nintendo Wii game controller. And, you can pick up a free limited edition poster that we collaborated with DOW to produce.

"Limited Edition"

And speaking of TechXPOTS, meet Dick James, Chipworks’ Senior Technology Analyst. He’s been invited to present "What's Inside the Market Leading Accelerometers and Gyroscopes" at the Emerging Markets and Technologies TechXPOT on July 18, 2007 @ 12:30 pm. Be sure to get there on time to ensure a seat. Dick’s presentations tend to get quite crowded.

Our MEMS market partner – Yole Developpement - will also be there. Yole is exhibiting in booth 8352 on the same floor as us, and Jean-Christophe Eloy, general manager and Founder of Yole will be presenting “MEMS Markets are Going Consumer: Impact on Equipment and Materials Business for MEMS Production” in the MEMS Business Models TechXPOT at 3:00 pm on July 18, 2007.

If it’s July, it’s time for Semicon West…we’ll see you inside technology…in San Francisco. 

Contributed by St.J. Dixon-Warren, Manager Technical Intelligence Process Engineering

Infineon Silicon Art ‘maps’ out the source

As mentioned previously in our blog, Chipworks often finds curious silicon art, especially on analog parts. Perhaps this says something about the temperament of analog designers.

In this case, we have found some wonderful examples on the Infineon PMB7870 E-GOLD^TMradio - PMB 7870. This chip is a smart solution for entry mobile phones.The PMB7870 die, shown below, is 5.85 mm x 5.47 mm within the die seals.

<click to enlarge image>

The silicon art found on the die starts with the Infineon motto “Never stop thinking”:<click to enlarge image>

And the silicon art also suggests that someone is very thankful to their R&D group in Sophia-Antipolis:

<click to enlarge image>

Sophia-Antipolis is a technology park northwest of Antibes and southwest of Nice, France. This R&D centre specialises in wireless base band ICs, design flow, and speech recognition ICs.

<click to enlarge image>
Clearly, the folks that designed the chip are members of the RF Design Group:

<click to enlarge image>
This design group is likely located in North Rhine-Westphalia, given the nice Coat of Arms found on the die.

<click to enlarge image>
A little bit of digging on the Infineon website found the R&D centre at Duisburg, and putting the address into Google earth shows their building:

Which solves the question of what that weird logo is!

A press release from last year confirms most of this – according to Prof. Hermann Eul, Member of the Infineon Management Board and head of the Communication Solutions Business Group; “Our developers in Duisburg and in Sophia-Antipolis have achieved something truly exceptional. With E-GOLDvoice and fewer than 50 other electronic components, it’s now possible for the first time to manufacture mobile phones that fit their entire GSM functionality onto a circuit board measuring four square centimeters.”

So, if we’d looked at the release first, we would have saved a lot of time digging into the reasons for the die markings; maybe this says something about the temperament of reverse engineers – the search is half the fun!

The Day of Reckoning

Last week I took the rash step of publishing what we expected to see in the iPhone, so this week is when we find out how right or wrong we were. Overall, I don’t think we did too badly – see the table below:

We haven’t tracked down most of the modular parts such as the camera lens or PCBs, mostly because they are either un-marked, or the markings on them are obscure, to say the least.

When it comes to the chips, though, we did fairly well. All of the major ICs such the baseband processor, the image sensor, and NAND flash memory were what we expected, and the surprises are in areas such as the amount of power management silicon and the use of a Peregrine SoS (silicon-on-sapphire) RF- switch IC.

Another discovery was the separate nature of the touch screen and the LCD – for some reason I had assumed that they would be integrated into one unit. Of course that means an applications processor for the touchscreen, and more silicon for the LCD. National got the design win for that at both ends (board and glass), using the low-power, low-noise Mobile Pixel Link interface. For more details, see this article on the Video/Imaging Design Line website.

One of the hyped advantages of the iPhone is its battery life, so it’s not surprising that we have three dedicated power management chips in there, as well as the National devices.

I had forgotten about the firmware memory earlier, usually stored in NOR flash, but Apple multi-sources commodity chips such as those, so Intel and SST are not a surprise either. And it appears that the “confident body language” from Wolfson management reported earlier in the year was justified.

The position sensor as expected is a MEMS device, from STMicroelectronics. The LIS302D is a 3-axis - ±2g/±8g smart digital output accelerometer, with the discrete MEMS sensor co-packaged with a separate CMOS interface chip. And of course we happened to look at an LIS302D a few months ago.

STMicroelectronics Accelerometer from iPhone (left), and Chipworks in-house. (Click to enlarge)

Taking the lid off the MEMS chip shows what appears to be an x-y sensor on the right, and a z-axis sensor on the left.

Inside the LIS302D MEMS (Click to enlarge)

We had thought that the sensor may have been the same as the one used in the Nintendo Wii, since the part numbers are similar (LIS302D vs LIS3L02AE), and they are all 3-axis accelerometers but taking the lids off reveals noticeable differences. Maybe we’ll discuss those in another blog!

Getting back to the Peregrine part, theirs is a typical Silicon Valley story. They were founded in 1990, as a spin-off from the US Navy NELC lab, to commercialise their patented UTSi (Ultra-thin silicon) CMOS technology (originating from Hewlett Packard), targeted on the high-frequency RF and radiation-hard IC business.

Things ticked over quietly for some years, slowly growing the business as CMOS moved into the rad-hard area. In 2000 they bought the old (1987) Quality Semiconductor fab in Sydney, Australia, which had been acquired by IDT in 1999. This was a 6”, 0.25-µm fab, and by then 6” sapphire substrates were available, so a good opportunity to go to commercial scale.

In the meantime, of course the need for low-leakage RF IC products has grown exponentially, if not hyperbolically, and it would seem that Peregrine has hit the sweet spot with the mobile/cellphone market. They have signed a volume foundry agreement with Oki semiconductor in Japan, and recently announced record production volumes. Their products have appeared in a number of phones in the last few years, and now they’ve got a socket in the most hyped phone ever.

As it happens, we looked at a Peregrine UltraCMOS™ PE4268 switch a couple of years ago, and the UTSi process is one of those interesting niche processes that we come across once in a while. The technology at 0.5 and 0.25 µm is not high-end in lithography terms, but growing decent quality silicon 90 – 100 nm thick is.

The SoS layer is not perfect single crystal, but large-grain polycrystalline, and thermally treated to reduce the defects caused by the crystalline mismatch with the substrate. If you look closely at the transistor cross-section, you can see the occasional defect, but overall it’s pretty decent quality.

TEM Cross-Section of SoS Transistor (Click to enlarge)

TEM diffraction analysis of the epi-silicon on the sapphire shows that it is conventionally oriented, with a <100> surface, and <110> channel orientation. In the images below, the sapphire substrate is oriented with the <241> direction being into the page, nearly coincident with the Si <110> direction.

TEM Diffraction Images of Sapphire and Silicon Crystalline Structures (Click to enlarge)

So the guys at Peregrine have done a pretty good job on turning some fairly obscure work out of HP in the ‘70s into a leading-edge commercial technology. Good luck to them!

The Apple marketing juggernaut has been working overtime in the last six months, and it's finally here...Friday's iPhone day! All of the 164 Apple retail stores in the US will close at 2pm, re-opening at 6pm and staying open until midnight. AT&T have hired 2000 temporary staff for the launch, since their stores will also be carrying them, but not resellers – they’ve even put up a store-locator website to avoid confusion as to which stores have stock.

For those that are determined to buy one – this will not be cheap exercise; presumably, on top of the$499 or $599 cost of the phone, AT&T requires a two-year contract, at monthly rates of $60, $80, or $100, plus an “activation charge” of $36 – add all that up and it comes to a minimum of $1975, plus whatever state retail taxes apply.

Then of course you can buy a Bluetooth headset for another $120, a $25 protective case, a $35 hip case, a $30 armband, and last but not least, a $12.95 pack of anti-glare screen protectors.

Even at these prices, everyone is predicting a sell-out. The queues started in New York on Tuesday morning, but nobody is saying how many will be in stock.  Recently there was comment on