IEDM Next Week!
This has also been posted on our Chipworks Inside Angle blogsite.
In a few days time the great and the good of the electron device world will be gathering in Baltimore for the 2009 IEEE International Electron Devices Meeting. To quote the conference lead release, “IEDM is the world’s premier forum for the presentation of applied research in microelectronic, nanoelectronic and bioelectronic devices.”
From my perspective, focused on chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.
In the last few days I’ve gone through the advance program, and here’s my pick of what I want to try and get to, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.
Monday morning we have the plenary session, and we get to the delegates’ papers after lunch. Session 5 on memory technology is dominated by Numonyx, with three out of seven papers (5.1, 5.3, and 5.7), on their phase-change memory (PCM) technology. Since we looked at their 90-nm 128 Mb PCM part earlier this year, I’ll be sure to take those in, especially the last paper of the session which discusses their 45-nm 1-Gb part.
Tuesday morning there’s another bunch of memory papers; IBM continues (11.1) the scaling of their embedded trench DRAM to the 32-nm node; and in paper 11.6 Qualcomm and TSMC are looking at 45-nm MRAM.
There is also a session on 3D technology, with TSMC (14.1) discussing through-silicon vias (TSVs), and a paper by Fujitsu et al (14.6) on ultra-thinning wafers down to 7 µm. Back at Semicon West, Jerry Bautista of Intel put up this slide of their Terascale project packaging:
It probably doesn’t show too well in a web image, but the wafer in the cross-section at the bottom right is about eight microns thick. And given Samsung’s recent announcement of 15-µm thick dice in eight-stack flash-memories, we’re in for some super-thin chips in the not too distant future.
In the afternoon there’s a special session of invited papers on the design issues created by advanced CMOS processing (also known as design-for-manufacturability, or DFM), something that we’ve noticed and commented on in the recent generations of chips. In fact, this topic is hot enough that we’ve drafted a DFM report on the Intel 32-nm. Session speakers are from IBM, Intel, TSMC, and NEC, and others.
In parallel sessions we have a SWOT (strengths, weaknesses, opportunities, threats) analysis from IMEC of germanium as a channel material (19.3), and a Sony paper (22.8) on a 0.9-µm pitch image sensor, designing using a “constant-light-diffraction-scaling methodology”.
Come Wednesday, the last day of the conference doesn’t slow down. The morning is filled with advanced CMOS papers, two from Intel (28.1 and 28.4), and others from the IBM consortium (28.2) and UMC (28.3). I have to say I’m looking forward to the second Intel paper, to see if there’s any clarification on the NMOS stress mechanisms in their 2nd generation HKMG process.
After my blog back in October, I’ve come to the conclusion that we don’t have e-SiC; talking to other folks in the business, it seems that it’s still too difficult to get the carbon to stay in place in the silicon lattice; and we can’t see any carbon that is definitively associated with the source/drains. Hopefully we’ll find out next week!
In another morning session 27, on 3D memory, there’s a joint Intel/Numonyx PCM paper, and an invited review paper by Al Fazio, also from Intel.
Even though folks tend to take off home in the afternoon, I shall be there until the bitter end - session 34 is on flash memory, with reliability papers by Samsung (34.2), Toshiba (34.4), and Macronix (34.6). Parallel session 36 covers off the interconnect stack, with three NEC presentations of note (36.1 - with Toshiba, 36.4, and 36.5).
So as always, no peace for the curious! And I have to blow my own trumpet a bit, since I will be hosting the annual Chipworks ‘Lunch and Learn’ across the courtyard at the Marriott on Monday December 7th at 12.00 noon. We’ll be discussing some of the year’s chips, likely the ATI/TSMC 40-nm part, maybe a Freescale/IBM 45-nm chip, and of course we’ll have some of the details we found in Intel’s 32-nm Westmere part. For anyone that want to come along, registration is here, or at the door.
Update: we’re not the only ones hosting at the Marriott - Applied Materials is holding a symposium on the future of NAND flash on Tuesday evening, and ASM is having a lunch seminar on ALD on Wednesday. It will be a busy conference - hope to see you there!